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| S71WS512NE0BFWZZ Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory and Pseudo-Static RAM ADVANCE INFORMATION DISTINCTIVE CHARACTERISTICS MCP Features Operating Voltage Range of 1.65 to 1.95 V High Performance -- Speed: 54MHz Packages -- 96-ball FBGA--9 x 12 mm Operating Temperatures -- Wireless: -25C to +85C GENERAL DESCRIPTION The S71WS512 Series is a product line of stacked Multi-Chip Products (MCP) and consists of One or more S29WS256N (Simultaneous Operation, Burst Mode) Flash Die pSRAM options -- 128Mb pSRAM The products covered by this document are listed below. For details about their specifications, please refer to the individual constituent data sheets for further details. Number of S29WSxxxN 2 Total Flash Density 512Mb pSRAM Density 256Mb MCP S71WS512NE0 Notes: 1. This MCP is only guaranteed to operate @ 1.65 - 1.95 V regardless of component operating ranges. Publication Number S71WS512NE0BFWZZ_00 Revision A Amendment 1 Issue Date June 28, 2004 Advance Information Product Selector Guide Device-Model # S71WS512NE0BFWZZ SRAM/pSRAM Density 256Mb SRAM/pSRAM Type pSRAM - x16 Supplier COSMORAM 1 Flash Access RAM Access Time (MHz) Time (MHz) 54 54 Packages TBD 2 S71WS512NE0BFWZZ S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advance Information TABLE OF CONTENTS S71WS512NE0BFWZZ Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MCP Block Diagram of S71WS512NE0BFWZZ ...........................................6 Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode .............................................................................................33 Lock Register ....................................................................................................... 34 Table 6. Lock Register ........................................................ 34 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Connection Diagram of S71WS512NE0BFWZZ ..........................................7 Special Package Handling Instructions ........................................................8 Pin Description ..................................................................................................8 Logic Symbol .....................................................................................................9 Device Bus Operation ....................................................................................... 10 Table 1. Device Bus Operations ........................................... 10 Pin Capacitance ................................................................................................... 12 Physical Dimensions TBD . . . . . . . . . . . . . . . . . . 13 XXX .........................................................................................................................13 Hardware Data Protection Mode ................................................................. 34 Write Protect (WP#) ................................................................................... 34 Low VCC Write Inhibit ................................................................................. 34 Write Pulse "Glitch" Protection ............................................................... 35 Logical Inhibit ................................................................................................... 35 Power-Up Write Inhibit ............................................................................... 35 Standby Mode ...................................................................................................... 35 Automatic Sleep Mode ..................................................................................... 35 RESET#: Hardware Reset Input ................................................................ 35 Output Disable Mode ................................................................................... 36 SecSiTM (Secured Silicon) Sector Flash Memory Region .......................... 36 Factory Locked: Factor SecSi Sector Programmed and Protected At the Factory ....................................................................................................... 36 Table 7. SecSiTM Sector Addresses ........................................ 37 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) Distinctive Characteristics . . . . . . . . . . . . . . . . . . 14 General Description . . . . . . . . . . . . . . . . . . . . . . . . 16 Product Selector Guide . . . . . . . . . . . . . . . . . . . . 19 Block Diagram .................................................................................................... 19 Customer SecSi Sector ................................................................................. 37 SecSi Sector Protection Bit ......................................................................... 37 Common Flash Memory Interface (CFI) . . . . . . 37 Table 8. CFI Query Identification String ................................ 38 Table 9. System Interface String ......................................... 38 Table 10. Device Geometry Definition ................................... 39 Table 11. Primary Vendor-Specific Extended Query ................ 39 Table 12. Sector Address / Memory Address Map for the WS256N ........................................................................................ 41 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 21 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 23 Table 2. Device Bus Operations ........................................... 23 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 49 Reading Array Data ...........................................................................................49 Set Configuration Register Command Sequence .....................................49 Read Configuration Register Command Sequence ..................................50 Figure 1. Synchronous/Asynchronous State Diagram.............. 50 Requirements for Asynchronous Read Operation (Non-Burst) ..........23 Requirements for Synchronous (Burst) Read Operation ...................... 24 Table 3. Address Dependent Additional Latency ..................... 24 Read Mode Setting .........................................................................................50 Programmable Wait State Configuration ...............................................50 Table 13. Programmable Wait State Settings ......................... 51 Continuous Burst ........................................................................................... 24 8-, 16-, and 32-Word Linear Burst with Wrap Around ......................25 Table 4. Burst Address Groups ............................................ 25 Programmable Wait State ............................................................................ 51 Boundary Crossing Latency ......................................................................... 51 Set Internal Clock Frequency ...................................................................... 51 Table 14. Wait States for Handshaking ................................. 51 8-, 16-, and 32-Word Linear Burst without Wrap Around ................25 Configuration Register ......................................................................................25 Handshaking ..........................................................................................................25 Simultaneous Read/Write Operations with Zero Latency ................... 26 Writing Commands/Command Sequences ................................................ 26 Unlock Bypass Mode .................................................................................... 26 Accelerated Program/Erase Operations ..................................................... 26 Write Buffer Programming Operation .........................................................27 Autoselect Mode ................................................................................................ 28 Advanced Sector Protection and Unprotection ....................................... 29 Persistent Mode Lock Bit ............................................................................ 29 Password Mode Lock Bit ............................................................................. 30 Sector Protection ............................................................................................... 30 Persistent Sector Protection .......................................................................... 30 Persistent Protection Bit (PPB) ...................................................................31 Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode ..............................................................................................31 Dynamic Protection Bit (DYB) ....................................................................31 Table 5. Sector Protection Schemes ..................................... 32 Handshaking ...................................................................................................... 51 Burst Sequence ............................................................................................... 52 Burst Length Configuration ......................................................................... 52 Table 15. Burst Length Configuration ................................... 52 Burst Wrap Around ...................................................................................... 52 Burst Active Clock Edge Configuration .................................................. 52 RDY Configuration ........................................................................................ 52 RDY Polarity .................................................................................................... 52 Configuration Register ...................................................................................... 53 Table 16. Configuration Register .......................................... 53 Reset Command ................................................................................................. 53 Autoselect Command Sequence .................................................................... 54 Table 17. Autoselect Addresses ........................................... 54 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence ................ 55 Word Program Command Sequence ........................................................... 55 Write Buffer Programming Command Sequence ..................................... 56 Table 18. Write Buffer Command Sequence .......................... 56 Figure 2. Write Buffer Programming Operation ...................... 57 Password Sector Protection ............................................................................33 64-bit Password ...............................................................................................33 Unlock Bypass Command Sequence ........................................................ 57 Figure 3. Program Operation ............................................... 58 June 28, 2004 S71WS512NE0BFWZZ_00_A1 3 Advance Information Chip Erase Command Sequence ................................................................... 58 Sector Erase Command Sequence .................................................................59 Erase Suspend/Erase Resume Commands .................................................. 60 Figure 4. Erase Operation.................................................... 61 Program Suspend/Program Resume Commands ...................................... 61 Lock Register Command Set Definitions ................................................... 62 Password Protection Command Set Definitions ..................................... 62 Non-Volatile Sector Protection Command Set Definitions ..................63 Global Volatile Sector Protection Freeze Command Set ..................... 64 Volatile Sector Protection Command Set ...................................................65 SecSi Sector Entry Command .........................................................................65 Command Definition Summary ..................................................................... 66 Write Operation Status . . . . . . . . . . . . . . . . . . . . .69 DQ7: Data# Polling ........................................................................................... 69 Figure 5. Data# Polling Algorithm......................................... 70 Figure 22. Synchronous Program Operation Timings: CLK Latched Addresses......................................................................... 88 Figure 23. Accelerated Unlock Bypass Programming Timing..... 88 Figure 24. Data# Polling Timings (During Embedded Algorithm) ... ........................................................................................ 89 Figure 25. Toggle Bit Timings (During Embedded Algorithm) ... 89 Figure 26. Synchronous Data Polling Timings/Toggle Bit Timings .. ........................................................................................ 90 Figure 27. DQ2 vs. DQ6 ..................................................... 90 Figure 28. Latency with Boundary Crossing when Frequency > 66 MHz................................................................................. 91 Figure 29. Latency with Boundary Crossing into Program/Erase Bank................................................................................ 91 Figure 30. Example of Wait States Insertion.......................... 92 Figure 31. Back-to-Back Read/Write Cycle Timings ................ 92 Erase and Programming Performance . . . . . . . . 93 RDY: Ready .......................................................................................................... 70 DQ6: Toggle Bit I ............................................................................................... 70 Figure 6. Toggle Bit Algorithm.............................................. 71 128Mb pSRAM FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 FUNCTION TRUTH TABLE . . . . . . . . . . . . . . . 95 Asynchronous Operation (Page Mode) ..................................................... 95 DQ2: Toggle Bit II ...............................................................................................72 Table 19. DQ6 and DQ2 Indications ..................................... 72 Reading Toggle Bits DQ6/DQ2 ......................................................................72 DQ5: Exceeded Timing Limits ........................................................................73 DQ3: Sector Erase Timer .................................................................................73 DQ1: Write to Buffer Abort ............................................................................73 Table 20. Write Operation Status ......................................... 74 FUNCTION TRUTH TABLE (Continued) . . . . 96 Synchronous Operation (Burst Mode) .......................................................96 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 75 Figure 7. Maximum Negative Overshoot Waveform................. 75 Figure 8. Maximum Positive Overshoot Waveform .................. 75 STATE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . 97 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 98 Power-up ...............................................................................................................98 Configuration Register ......................................................................................98 CR Set Sequence ................................................................................................98 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 75 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .76 CMOS Compatible .............................................................................................76 Test Conditions ...................................................................................................77 Figure 9. Test Setup ........................................................... 77 Table 21. Test Specifications ............................................... 77 FUNCTIONAL DESCRIPTION (Continued) . . 99 Address Key .........................................................................................................99 FUNCTIONAL DESCRIPTION (Continued) . 100 Power Down ...................................................................................................... 100 FUNCTIONAL DESCRIPTION (Continued) . . 101 Burst Read/Write Operation ..........................................................................101 Switching Waveforms ........................................................................................77 Table 22. Key to Switching Waveforms ................................. 77 Figure 10. Input Waveforms and Measurement Levels............. 77 FUNCTIONAL DESCRIPTION (Continued) . 102 CLK Input Function ..........................................................................................102 ADV# Input Function .......................................................................................102 WAIT# Output Function ................................................................................102 VCC Power-up ..................................................................................................... 78 Pin Capacitance .................................................................................................. 78 Figure 11. VCC Power-up Diagram ........................................ 78 AC Characteristics--Synchronous . . . . . . . . . . . 79 CLK Characterization ........................................................................................79 Figure 12. CLK Characterization ........................................... 79 FUNCTIONAL DESCRIPTION (Continued) . . 103 Latency ..................................................................................................................103 FUNCTIONAL DESCRIPTION (Continued) . 104 Address Latch by ADV# .................................................................................104 Burst Length ........................................................................................................104 Single Write .........................................................................................................104 Write Control ....................................................................................................105 Synchronous/Burst Read @ VIO = 1.8 V ..................................................... 80 Timing Diagrams .................................................................................................. 81 Figure 13. CLK Synchronous Burst Mode Read (rising active CLK). ....................................................................................... 81 Figure 14. Synchronous Burst Mode Read.............................. 82 Figure 15. Eight-word Linear Burst with Wrap Around ............. 82 Figure 16. Eight-word Linear Burst without Wrap Around......... 83 Figure 17. Linear Burst with RDY Set One Cycle Before Data.... 83 FUNCTIONAL DESCRIPTION (Continued) . 106 Burst Read Suspend ..........................................................................................106 Burst Write Suspend ........................................................................................106 FUNCTIONAL DESCRIPTION (Continued) . . 107 Burst Read Termination ..................................................................................107 Burst Write Termination ................................................................................107 AC Characteristics--Asynchronous . . . . . . . . . . 84 Asynchronous Mode Read @ VIOpS = 1.8 V ............................................. 84 Timing Diagrams ................................................................................................. 84 Figure 18. Asynchronous Mode Read with Latched Addresses... 84 Figure 19. Asynchronous Mode Read..................................... 85 Hardware Reset (RESET#) .............................................................................. 85 Figure 20. Reset Timings..................................................... 85 ABSOLUTE MAXIMUM RATINGS (See WARNING below.) . . . . . . . . . . . . . . . . . . . . . . 108 RECOMMENDED OPERATING CONDITIONS (See WARNING below.) . . . . . . . . . . . . . . . . . . 108 (Referenced to VSS) ................................................................................... 108 Erase/Program Operations @ VIO = 1.8 V ................................................. 86 Figure 21. Asynchronous Program Operation Timings: WE# Latched Addresses ............................................................. 87 DC CHARACTERISTICS . . . . . (Under Recommended Operating Conditions unless otherwise noted) . . . . . . . . Note *1,*2,*3 109 S71WS512NE0BFWZZ_00_A1 June 28, 2004 4 Advance Information AC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted) . . . . . . . . . . . . . . . . . . . . 110 ASYNCHRONOUS READ OPERATION (PAGE MODE) ................110 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 124 Asynchronous Read / Write Timing #1-1 (CE#1 Control) ...................124 Asynchronous Read / Write Timing #1-2 (CE#1 / WE# / OE# Control) ..................................................................................................................................124 AC CHARACTERISTICS (Continued) . . . . . . . . 111 ASYNCHRONOUS WRITE OPERATION ............................................. 111 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 125 Asynchronous Read / Write Timing #2 (OE#, WE# Control) ........125 Asynchronous Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) ..................................................................................................................................125 AC CHARACTERISTICS (Continued) . . . . . . . . 112 SYNCHRONOUS OPERATION - CLOCK INPUT (BURST MODE) .................................................................................................................................. 112 SYNCHRONOUS OPERATION - ADDRESS LATCH (BURST MODE) .................................................................................................................................. 112 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 126 Clock Input Timing ..........................................................................................126 Address Latch Timing (Synchronous Mode) ............................................126 AC CHARACTERISTICS (Continued) . . . . . . . . 113 SYNCHRONOUS READ OPERATION (BURST MODE) ................ 113 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 127 Synchronous Read Timing #1 (OE# Control) .........................................127 AC CHARACTERISTICS (Continued) . . . . . . . . 114 SYNCHRONOUS WRITE OPERATION (BURST MODE) .............. 114 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 128 Synchronous Read Timing #2 (CE#1 Control) ........................................128 AC CHARACTERISTICS (Continued) . . . . . . . . 115 POWER DOWN PARAMETERS ............................................................... 115 OTHER TIMING PARAMETERS ................................................................. 115 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 129 Synchronous Read Timing #3 (ADV# Control) .....................................129 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 130 Synchronous Write Timing #1 (WE# Level Control) ...........................130 AC CHARACTERISTICS (Continued) . . . . . . . . 116 AC TEST CONDITIONS ............................................................................... 116 AC MEASUREMENT OUTPUT LOAD CIRCUIT ................................. 116 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 131 Synchronous Write Timing #2 (WE# Single Clock Pulse Control) .. 131 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . 117 Asynchronous Read Timing #1-1 (Basic Timing) ...................................... 117 Asynchronous Read Timing #1-2 (Basic Timing) ...................................... 117 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 132 Synchronous Write Timing #3 (ADV# Control) ...................................132 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 133 Synchronous Write Timing #4 (WE# Level Control, Single Write) 133 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 118 Asynchronous Read Timing #2 (OE# & Address Access) ...................118 Asynchronous Read Timing #3 (LB# / UB# Byte Access) ..................118 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 134 Synchronous Read to Write Timing #1(CE#1 Control) .......................134 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 119 Asynchronous Read Timing #4 (Page Address Access after CE#1 Control Access) .................................................................................................................. 119 Asynchronous Read Timing #5 (Random and Page Address Access) 119 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 135 Synchronous Read to Write Timing #2(ADV# Control) .................... 135 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 136 Synchronous Write to Read Timing #1 (CE#1 Control) ......................136 TIMING DIAGRAMS (Continued) . . . . . . . . . . 120 Asynchronous Write Timing #1-1 (Basic Timing) ...................................120 Asynchronous Write Timing #1-2 (Basic Timing) ...................................120 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 137 Synchronous Write to Read Timing #2 (ADV# Control) .................. 137 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 121 Asynchronous Write Timing #2 (WE# Control) ................................... 121 Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control) ........................................................................................................................ 121 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 138 POWER-UP Timing #1 ....................................................................................138 POWER-UP Timing #2 ...................................................................................138 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 139 POWER DOWN Entry and Exit Timing ..................................................139 Standby Entry Timing after Read or Write ..............................................139 TIMING DIAGRAMS (Continued) . . . . . . . . . . 122 Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control) ....................................................................................................................... 122 Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control) ....................................................................................................................... 122 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 140 Configuration Register Set Timing #1 (Asynchronous Operation) ...140 TIMING DIAGRAMS (Continued) . . . . . . . . . . . 141 Configuration Register Set Timing #2 (Synchronous Operation) .....141 TIMING DIAGRAMS (Continued) . . . . . . . . . . 123 Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control) ....................................................................................................................... 123 Revision Summary June 28, 2004 S71WS512NE0BFWZZ_00_A1 5 Advance Information Block Diagrams MCP Block Diagram of S71WS512NE0BFWZZ VCCf_1 A23 to A0 VSS AVD# CLK WE# OE# RESET# 256 M bit Burst Flash Memory_1 RDY CE#f1 VCCf_2 A23 to A0 VSS 256 M bit Burst Flash Memory_2 ACC WP# CE#f2 DQ15 to DQ0 VCCpS VSS VIOpS A22 to A0 128 M bit pSRAM_1 LB# UB# CE#1pS-1 CE2pS-1 VCCpS VSS VIOpS 128 M bit pSRAM_2 CE#1pS-2 CE2pS-2 6 S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advance Information Connection Diagrams Connection Diagram of S71WS512NE0BFWZZ 96-Ball FBGA Top View A1 NC A2 NC A9 NC A10 NC B1 NC B2 NC B9 NC B10 NC C2 AVD# C3 VSS C4 CLK C5 CE#f2 C6 RFU C7 RFU C8 RFU C9 RFU D2 WP# D3 A7 D4 LB# D5 ACC D6 WE# D7 A8 D8 A11 D9 RFU E2 A3 E3 A6 E4 UB#s E5 F5 RDY E6 F6 A20 E7 A19 E8 A12 E9 A15 RST#f CE2pS_1 F2 A2 F3 A5 F4 A18 F7 A9 F8 A13 F9 A21 G2 A1 G3 A4 G4 A17 G5 CE#1pS2 G6 A23 G7 A10 G8 A14 G9 A22 H2 A0 H3 VSS H4 DQ1 H5 J5 DQ3 H6 J6 DQ4 H7 DQ6 H8 RFU H9 A16 VCCpS CE2pS_2 J2 CE#f1 J3 OE# J4 DQ9 J7 DQ13 J8 DQ15 J9 RFU K2 L2 RFU K3 L3 DQ8 K4 DQ10 K5 VCCf_1 K6 VIOpS K7 DQ12 K8 DQ7 K9 VSS CE#1pS_1 DQ0 L4 DQ2 L5 DQ11 L6 RFU L7 DQ5 L8 DQ14 L9 RFU M2 RFU M3 RFU M4 VSS M5 VCC f_2 M6 RFU M7 RFU M8 RFU M9 RFU N1 NC N2 NC N9 NC N10 NC P1 NC P2 NC P9 NC P10 NC June 28, 2004 S71WS512NE0BFWZZ_00_A1 7 Advance Information Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (FBGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Pin Description A22-A0 A23 DQ15-DQ0 CE#f CE#1pS CE#2pS OE# WE# RDY CLK AVD# UB# LB# RESET# WP# ACC VCCf VCCps VIOps Vss NC RFU = = = = = = = = = = = = = = = = = 23 Address Inputs (Common) 1 Address Inputs (Flash) 16 Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable1 (pSRAM) Chip Enable2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready Output Clock Input Address Valid Input Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin, Active Low (Flash) Hardware Write Protect (Flash) Acceleration pin (Flash) Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply pSRAM Output buffer Power Supply Device Ground (Common) Pin Not Connected Internally Reserved for Future Use = = = = = 8 S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advance Information Logic Symbol 23 A22-A0 A23 CE#f CE1#pS CE2s OE# WE# WP#/ACC RESET# UB# LB# RDY DQ15-DQ0 16 NOR Flash and pSRAM and DATA STORAGE densities up to 4 Gigabits The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package outline may vary. Any pinout in any MCP, however, will be a subset of the pinout above. In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, the user is recommended to treat them as reserved and not connect them to any other signal. For any further inquiries about the above look-ahead pinout, please refer to the application note on this subject or contact your sales office. June 28, 2004 S71WS512NE0BFWZZ_00_A1 9 Advance Information Device Bus Operation Table 1. Operation (Asynchronous) - Flash Read - Address Latched Read - Address Steady State Write Standby Reset Output Disable Device Bus Operations WE# H H L X X H CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# L H L H L H H X H H L H L H L H L H X H L H H H H H H H H X L H H L H L H L H H X H H H H H H H H H H X H H H L H L H L H H X H H H H L L H X X Addr Valid Valid Valid X X X DQ15DQ0 Valid Valid Valid High-Z High-Z X UB# X X X X X X LB# X X X X X X RESET# WP# H H H H L H H H H H H H ACC# H H H H H H CLK(See Note) AVD# X X X X X X L L X X X Operation(Synchronous) Flash CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# Load Starting Burst Adress Advance Burst Read to Next Address Terminate current Burst read cycle "Terminate current Burst read cycle via RESET#" "Terminate current Burst read cycle and start new Burst read cycle" WE# H H H H H Addr Valid X X X Valid DQ15DQ0 Data Data High-Z High-Z Valid UB# X X X X X LB# X X X X X RESET# WP# H H H L H H H H H H ACC# H H H H H CLK(See Note) AVD# L H L H H X L H H L H L H X H L H H H H H X H H L H L H H X L H H H H H H X H H L H L H H X L H X L X X X H X X X Operation (Asyncronous) - pSRAM Read Read (Page) Write CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# H H H H H H H H H H H H H H H H H H H H L H L H L H L H L H H X L H H H H H H H H H H H L H H L H L H L H L H L H X L H H H H H H H H H H H H H H H H L H H X H H H H L L H WE# H H L Addr Valid Valid Valid DQ15DQ0 Valid Valid Valid Invalid( DQ0-8) Valid(DQ 9-15) Valid(DQ 0-8) Invalid( DQ9-15) High-Z High-Z X UB# L H/L L LB# L H/L L RESET# WP# H H H H H H ACC# H H H CLK(See Note) AVD# X X X H/L H/L *note Write(Upper Byte) L Valid L H H H H X *note Write(Lower Byte) Standby PowerDown Output Disable L H X H Valid X X X H X X X L X X X H H H H H H H H H H H H X X X X *note *note X *note Operation(Syncronous) pSRAM CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE# Load Starting Burst Adress Advance Burst Read to Next Address Terminate current Burst read cycle "Terminate current Burst read cycle and start new Burst read cycle" WE# H H H H Addr Valid X X Valid DQ15DQ0 Data Data High-Z Valid UB# X X X X LB# X X X X RESET# WP# H H H H H H H H ACC# H H H H CLK(See Note) AVD# H H H H H H H H H H H H H H H H H H H H H L H L H H L H H H H H H H H H L H L H L H X L X X H X Legend: L = Logic 0, H = Logic 1, X = Don't Care. Note: Default active edge of CLK is the rising edge. Ordering Information 10 S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advance Information The order number (Valid Combination) is formed by the following: S 71 WS 512 NE 0 B F W ZZ 0 PACKING TYPE 0 2 3 = Tray = 7" Tape & Reel = 13" Tape & Reel Additional ordering options See Product Selector Guide TEMPERATURE (and RELIABILITY) GRADE E W I A F B 0 8 A B C E = Engineering Samples = Wireless (-25C to +85C) = Industrial (-40C to +85C) = Standard (Pb-free compliant) Package = Lead (Pb)-free Package = BGA Package = No second content = = = = = 8 Mb 16 Mb 32 Mb 64 Mb 256 Mb (two 128Mb) PACKAGE MATERIAL SET (BGA Package Type) PACKAGE TYPE CHIP CONTENTS--2 CHIP CONTENTS--1 Spansion FLASH MEMORY PROCESS TECHNOLOGY (Highest-density Flash described in Characters 4-8) N 512 S = 110 nm MirrorBitTM Technology = two S29WS256N = 1.8-volt VCC BASE NOR FLASH DENSITY BASE NOR FLASH CORE VOLTAGE BASE NOR FLASH INTERFACE and SIMULTANEOUS READ/ WRITE W 71 S = Simultaneous Read/Write, Burst = Flash Base + xRAM. = Spansion PRODUCT FAMILY PREFIX Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local sales office to confirm availability of specific valid combinations and to check on newly released combinations. June 28, 2004 S71WS512NE0BFWZZ_00_A1 11 Advance Information Valid Combinations Order Number S71WS512NE0BFWZZ Package Marking 71WS512NE0BFWZZ Flash Access Time (MHz) 54 (p)SRAM Access Time (MHz) 54 Temperature Range -25C to +85C Supplier Supplier 1 Pin Capacitance Symbol CIN1 CIN2 Cout Parameter Input Capacitance Output Capacitance Control Capacitance Test Condition VIN=0 Vout=0 VIN=0 Typ TBD TBD TBD Max TBD TBD TBD Unit pF pF pF 12 S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advance Information Physical Dimensions TBD XXX June 28, 2004 S71WS512NE0BFWZZ_00_A1 13 Advance Information S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) Distinctive Characteristics Architectural Advantages Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured on 110 nm MirrorBitTM process technology Simultaneous Read/Write operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency between read and write operations -- Sixteen bank architecture: Each bank consists of 16Mb (WS256N) Programable Burst Interface -- 2 Modes of Burst Read Operation -- Linear Burst: 32, 16, and 8 words with or without wrap-around -- Continuous Sequential Burst SecSiTM (Secured Silicon) Sector region -- 256 words accessible through a command sequence, 128 words for the Factory SecSi Sector and 128 words for the Customer SecSi Sector. Sector Architecture -- S29WS256N: Eight 16 Kword sectors and twohundred-fifty-four 64 Kword sectors -- Banks 0 and 15 each contain 16 Kword sectors and 64 Kword sectors; Other banks each contain 64 Kword sectors -- Eight 16 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range 100,000 erase cycles per sector typical 20-year data retention typical S29WS256N 256 Megabit (16 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Power dissipation (typical values, CL = 30 pF) @ 66 MHz -- Continuous Burst Mode Read: <28 mA -- Simultaneous Operation: <50 mA -- Program: <35 mA -- Erase: <35 mA -- Standby mode: <20 A Hardware Features Sector Protection -- Write protect (WP#) function allows protection of eight outermost boot sectors, four at top and four at bottom of memory, regardless of sector protect status Handshaking feature available -- Provides host system with minimum possible latency by monitoring RDY Hardware reset input (RESET#) -- Hardware method to reset the device for reading array data Boot Option -- Dual Boot CMOS compatible inputs, CMOS compatible outputs Low VCC write inhibit Security Features Advanced Sector Protection consists of the two following modes of operation Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector using a user-defined 64-bit password Performance Characteristics Read access times at 66/54 MHz @ 1.8V VIO (1.65 - 1.95V) -- Burst access times of 11.2/13.5 ns for 1.8V VIO (@ 30 pF at industrial temperature range) -- Synchronous initial latency of 69/69 ns for 1.8V VIO (@ 30 pF at industrial temperature range) -- Asynchronous random access times of 70/70 ns for 1.8V VIO (@ 30 pF at industrial temperature range) High Performance -- Typical word programming time of < 40 s -- Typical effective word programming time of <9.4 s utilizing a 32-Word Write Buffer at Vcc Level -- Typical effective word programming time of <4 s utilizing a 32-Word Write Buffer at ACC Level -- Typical sector erase time of <150 ms for both 16 Kword sectors and <400 ms sector erase time for 64 Kword sectors Software Features Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards Data# Polling and toggle bits -- Provides a software method of detecting program and erase operation completion 14 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Erase Suspend/Resume -- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Program Suspend/Resume -- Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences Additional Features Program Operation -- Ability to perform synchronous and asynchronous program operation independent of burst control register setting ACC input pin -- Acceleration function reduces programming time in a factory setting. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 15 Advance Information General Description The WSxxxN is a 256 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 16 Mwords of 16 bits. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 9.0volt VHH on ACC may be used for faster program performance if desired. The device can be programmed in standard EPROM programmers. At 66 MHz and 1.8V VIO, the device provides a burst access of 11.2 ns at 30 pF with am initial latency of 69 ns at 30 pF. At 54 MHz and 1.8V VIO, the device provides a burst access of 13.5 ns at 30 pF with an initial latency of 69 ns at 30 pF. The device operates within the industrial temperature range of -40C to +85C or wireless temperature range of -25C to +80C. These devices are offered in MCP compatible FBGA packages. See the product selector guide for details The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into sixteen banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Quantity of Sectors (WS256N) 4/4/4 15/7/3 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 16/8/4 15/7/3 4/4/4 Sector Size 16 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 16 Kwords The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a 16 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and then wrap or non-wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Write Buffer Programming algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. This feature provides superior programming performance by grouping locations being programmed.The Unlock Bypass mode facilitates faster program times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The Program Suspend/Program Resume feature enables the user to put program on hold for any period of time to read data from any sector that is not selected for programming. If a read is needed from the SecSi Sector area (One Time Program area), Persistent Protection area, Dynamic Protection area, or the CFI area, after an program suspend, then the user must use the proper command sequence to enter and exit this region. The program suspend/resume functionality is also available when programming in erase suspend (1 level depth only). The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area), Persistent Protection area, Dynamic Protection area, or the CFI area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase timer), and DQ1 (write to buffer abort). After a program or erase cycle has been completed, the device automatically returns to reading array data. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 17 Advance Information The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at VIL, WP# locks the four outermost boot sectors at the top of memory and four outermost boot sectors at the bottom of memory. When the ACC pin = VIL, the entire flash memory array is protected. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. SpansionTM Flash memory products combine years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. 18 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Product Selector Guide Part Number VIO Option Speed Option (Burst Frequency) (Note 1) Max Synchronous Latency, ns (tIACC) Max Synchronous Burst Access Time, ns (tBACC) Max Asynchronous Access Time tCE), ns Max CE# Access Time, ns (tCE), ns Max OE# Access Time, ns (tOE) 66 MHz 69 11.2 70 70 11.2 S29WS256N 1.65-1.95 V 54 MHz 69 13.5 70 70 13.5 Block Diagram VCC VSS VSSIO VIO RDY Buffer RDY Erase Voltage Generator Input/Output Buffers DQ15-DQ0 WE# RESET# WP# ACC State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE# OE# Y-Decoder VCC Detector Y-Gating Address Latch Timer X-Decoder Cell Matrix AVD# CLK Burst State Control Burst Address Counter Amax-A0* *WS256N: A23-A0 June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 19 Advance Information Block Diagram of Simultaneous Operation Circuit VCC VSS VIO Y-Decoder Bank Address Latches and Control Logic DQ15-DQ0 Bank 0 Amax-A0 X-Decoder OE# Bank Address Latches and Control Logic Y-Decoder DQ15-DQ0 Bank 1 WP# ACC RESET# WE# CE# AVD# RDY DQ15-DQ0 Amax-A0 X-Decoder DQ15-DQ0 Status STATE CONTROL & COMMAND REGISTER Amax-A0 Control X-Decoder Latches and Control Logic Y-Decoder Bank Address Bank 14 DQ15-DQ0 Amax-A0 Amax-A0 X-Decoder Bank Address Latches and Control Logic Y-Decoder Bank 15 DQ15-DQ0 Notes: Amax=A23 for the WS256N. 20 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Input/Output Descriptions A23-A0 DQ15-DQ0 CE# OE# WE# VCC VIO VSS VSSIO NC RDY CLK = = = = = = = = = = = = Address inputs for WS256N Data input/output Chip Enable input. Asynchronous relative to CLK for the Burst mode. Output Enable input. Asynchronous relative to CLK for the Burst mode. Write Enable input. Device Power Supply (1.65 - 1.95 V). Input & Output Buffer Power Supply (1.35 - 1.70 V). Ground Output Buffer Ground No Connect; not connected internally Ready output. Indicates the status of the Burst read. Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs Hardware reset input. Low = device resets and returns to reading array data Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. AVD# = RESET# WP# = = ACC = June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 21 Advance Information Logic Symbol Max*+1 Amax*-A0 CLK WP# ACC CE# OE# WE# RESET# AVD# RDY DQ15-DQ0 16 * max=23 for the WS256N. 22 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 2. Device Bus Operations CLK (See Note) X X X X X L L X X Operation Asynchronous Read - Addresses Latched Asynchronous Read - Addresses Steady State Asynchronous Write Synchronous Write Standby (CE#) Hardware Reset Burst Read Operations (Synchronous) Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle Legend: L = Logic 0, H = Logic 1, X = Don't Care. CE# L L L L H X L L H X L OE# L L H H X X X L X X X WE# H H L L X X H H H H H Addresses Addr In Addr In Addr In Addr In X X Addr In X X X Addr In DQ15-0 I/O I/O I/O I/O HIGH Z HIGH Z X Burst Data Out HIGH Z HIGH Z I/O RESET# H H H H H L H H H L H AVD# H X X X Note: Default active edge of CLK is the rising edge. Requirements for Asynchronous Read Operation (NonBurst) To read data from the memory array, the system must first assert a valid address on A23-A0 for WS256N , while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15-DQ0. Since the memory array is divided into sixteen banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 23 Advance Information Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst read and linear burst read of a preset length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration register command sequence. See "Set Configuration Register Command Sequence" section for further details. Once the system has written the "Set Configuration Register" command sequence, the device is enabled for synchronous reads only. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle at which point the internal address counter is automatically incremented. Note that the device has a fixed internal address boundary that occurs every 128 words, starting at address 00007Fh. No boundary crossing latency is required when the device operates at or below 66 MHz to reach address 000080h. When the device operates above 66 MHz, a boundary crossing of one additional wait state is required. The timing diagram can be found in Figure 28. When the starting burst address is not divisible by four, additional waits are required. For example, if the starting burst address is divisible by four A1:0 = 00, no additional wait state is required, but if the starting burst address is at address A1:0 = 01, 10, or 11, one, two or three wait states are required, respectively, until data DQ4 is read. The RDY output indicates this condition to the system by deasserting (see Table 3 and Table 13). Table 3. Initial Address A[10] 00 01 10 11 Address Dependent Additional Latency Cycle X DQ0 DQ1 DQ2 DQ3 X+1 DQ1 DQ2 DQ3 -- X+2 DQ2 DQ3 --- X+3 DQ3 ---- X+4 DQ4 DQ4 DQ4 DQ4 X+5 DQ5 DQ5 DQ5 DQ5 X+6 DQ6 DQ6 DQ6 DQ6 Continuous Burst The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 2. If the host system crosses a bank boundary while reading in burst mode, and the subsequent bank is not programming or erasing, a one-cycle latency is required as described above if the device is operating above 66 MHz. If the device is operating at or below 66 MHz, no boundary crossing latency is required. If the host system crosses the bank boundary while the subsequent bank is programming or erasing, the device will provide read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse. 24 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information 8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three burst read modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 4.) Table 4. Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words Burst Address Groups Group Address Ranges 0-7h, 8-Fh, 10-17h,... 0-Fh, 10-1Fh, 20-2Fh,... 00-1Fh, 20-3Fh, 40-5Fh,... For example, if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D3E-3F-38h if wrap around is enabled. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 128 words; thus, no wait states are inserted (except during the initial access). (See Figure 15) 8-, 16-, and 32-Word Linear Burst without Wrap Around If wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute linearly up to the maximum memory address of the selected number of words. The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. For example: if the starting address in the 8word mode is 39h, the address range to be read would be 39-40h, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-40 if wrap around is not enabled. The next address to be read will require a new address and AVD# pulse. The RDY pin indicates when data is valid on the bus. Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. For more information, see Table 16. Handshaking The device is equipped with a handshaking feature that allows the host system to simply monitor the RDY signal from the device to determine when the burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. See the "Set Configuration Register Command Sequence" section and the "Requirements for Synchronous (Burst) Read Operation" section for more information. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 25 Advance Information Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 31 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asynchronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored when the device is configured in the Asynchronous mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE# (see Table 16). An erase operation can erase one sector, multiple sectors, or the entire device. Table 12 indicates the address space that each sector occupies. The device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A "bank address" is the set of address bits required to uniquely select a bank. Similarly, a "sector address" is the address bits required to uniquely select a sector. ICC2 in "DC Characteristics" represents the active current specification for the write mode. "AC Characteristics--Synchronous" and "AC Characteristics--Asynchronous" contain timing specification tables and timing diagrams for write operations. Unlock Bypass Mode The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a set of words, instead of four. See the "Unlock Bypass Command Sequence" section for more details. Accelerated Program/Erase Operations The device offers accelerated program and accelerated chiperase operations through the ACC function. ACC is intended to allow faster manufacturing throughput at the factory and not to be used in system operations. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a "Write-to-Buffer-Abort Reset" is required while in Unlock By- 26 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information pass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions. Write Buffer Programming Operation Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard "word" programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. At this point, the system writes the number of "word locations minus 1" that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the "Program Buffer to Flash" confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (NOTE: the size of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the "writebuffer-page" address. All subsequent address/data pairs must fall within the "selected-write-buffer-page". The "write-buffer-page" is selected by using the addresses AMAX - A5 where AMAX is A23 for WS256N. The "write-buffer-page" addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple "write-buffer-pages". This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected "write-bufferpage", the operation will ABORT.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. Note that if a Write Buffer address location is loaded multiple times, the "address/ data pair" counter will be decremented for every data load operation. Also, the last data loaded at a location before the "Program Buffer to Flash" confirm command will be programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" command at the Sector Address. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 27 Advance Information Any other address/data write combinations will abort the Write Buffer Programming operation. The device will then "go busy." The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer "embedded" programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the "Number of Locations to Program" step. Write to an address in a sector different than the one specified during the "Write-Buffer-Load" command. Write an Address/Data pair to a different write-buffer-page than the one selected by the "Starting Address" during the "write buffer data loading" stage of the operation. Write data other than the "Confirm Command" after the specified number of "data load" cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the "last address location loaded"), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A "Write-to-Buffer-Abort reset" command sequence is required when using the Write-Buffer-Programming features in Unlock Bypass mode. Note that the SecSITM sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. However, programming the same word address multiple times without intervening erases requires a modified programming method. Please contact your local SpansionTM representative for details. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is approximately eight times faster than programming one word at a time. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (separate from the memory array) on DQ15-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. The autoselect codes can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 12). The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The autoselect codes can also be accessed in-system through the command register. The command sequence is illustrated in the "Command Definition Summary" sec- 28 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information tion. Note that if a Bank Address (BA) on the four uppermost address bits is asserted during the third write cycle of the autoselect command, the host system can read autoselect data from that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes, the host system must issue the autoselect command via the command register, as shown in the "Command Definition Summary" section. Refer to the "Autoselect Command Sequence" section for more information. Advanced Sector Protection and Unprotection This advanced security feature provides an additional level of protection to all sectors against inadvertant program or erase operations. The advanced sector protection feature disables both programming and erase operations in a sector while the advanced sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented using either or both of the two methods Hardware method Software method Persistent/Password Sector Protection is achieved by using the software method while the sector protection with WP# pin is achieved by using the hardware method. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. Persistent Mode Lock Bit Password Mode Lock Bit If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Mode Lock Bit. This will permanently set the part to operate using only Persistent Sector Protection. However, if the customer decides to use the Password Sector Protection method, they must set the Password Mode Lock Bit. This will permanently set the part to operate using only Password Sector Protection. It is important to remember that setting either the Persistent Mode Lock Bit or the Password Mode Lock Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. If both are selected to be set at the same time, the operation will abort. This is done so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Sector Protection Mode. The device is shipped with all sectors unprotected. Optional SpansionTM programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for more details. Persistent Mode Lock Bit A Persistent Mode Lock Bit exists to guarantee that the device remain in software sector protection. Once programmed (set to "0"), the Persistent Mode Lock Bit prevents programming of the Password Mode Lock Bit. This allows protection June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 29 Advance Information from potential hackers locking the device by placing the device in password sector protection mode and then changing the password accordingly. Password Mode Lock Bit In order to select the Password Sector Protection scheme, the customer must first program the password. Spansion LLC recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1.It permanently sets the device to operate using the Password Sector Protection Mode. It is not possible to reverse this function. 2.It also disables all further commands to the password region. All program and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Sector Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is after it is set. If the password is lost after setting the Password Mode Lock Bit, there will be no way to clear the PPB Lock Bit. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Lock Bit is not erasable. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. Sector Protection The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection: A software enabled command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection: A highly sophisticated software enabled protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection: A write protect pin (WP#) can prevent program or erase operations in the outermost sectors.The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Persistently Locked--A sector is protected and cannot be changed. Dynamically Locked--The sector is protected and can be changed by a simple command 30 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Unlocked--The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of "bits" namely Persistent Protection Bit (PPB), Dynamic Protecton Bit (DYB), and Persistent Protection Bit Lock (PPB Lock) are used to achieve the desired sector protection scheme Persistent Protection Bit (PPB) PPB is used to as an advanced security feature to protect individual sectors from being programmed or erased thereby providing additional level of protection. Every sector is assigned a Persistent Protection Bit. Each PPB is individually programmed through the PPB Program Command. However all PPBs are erased in parallel through the All PPB Erase Command. Prior to erasing, these bits dont have to be preprogrammed. The Embedded Erase algorithm automatically preprograms and verifies prior to an electrical erase. The system is not required to provide any controls or timings during these operations. The PPBs retain their state across power cycles because they are Non-Volatile. The PPBs have the same endurance as the flash memory. Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode PPB Lock Bit is a global volatile bit and provides an additional level of protection to the sectors. When programmed (set to "0"), all the PPBs are locked and hence none of them can be changed. When erased (cleared to "1"), the PPBs are changeable. There is only one PPB Lock Bit in every device. Only a hardware reset or a power-up clears the PPB Lock Bit. It is to be noted that there is no software solution, ie. command sequence to unlock the PPB Lock Bit. Once all PPBs are set (programmed to "0") to the desired settings, the PPB Lock Bit may be set (programmed to "0"). The PPB Lock Bit is set by issuing the PPB Lock Bit Set Command. Programming or setting the PPB Lock Bit disables program and erase commands to all the PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock Bit is to go through a hardward or powerup reset. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can disable the PPB Lock Bit to prevent any further changes to the PPBs during system operation. Dynamic Protection Bit (DYB) DYB is another security feature used to protect individual sectors from being programmed or erased inadvertantly. It is a volatile protection bit and is assigned to each sector. Each DYB can be individually modified through the DYB Set Command or the DYB Clear Command. The Protection Status for a particular sector is determined by the status of the PPB and the DYB relative to that sector. For the sectors that have the PPBs cleared (erased to "1"), the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Set or Clear command sequences, the DYBs will be set (programmed to "0") or cleared (erased to "1"), thus placing each sector in the protected or unprotected state respectively. These states are the so-called Dynamic Locked or Unlocked states due to the fact that they can switch back and forth between the protected and unprotected states. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set (programmed to "0") or cleared (erased to "1") as often as needed. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 31 Advance Information When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset, the DYBs are set or cleared depending upon the ordering option chosen. If the option to clear the DYBs after power up is chosen, (erased to "1"), then the sectors may be modified depending upon the PPB state of that sector. (See Table 5) If the option to set the DYBs after power up is chosen (programmed to "0"), then the sectors would be in the protected state. The PPB Lock Bit defaults to the cleared state (erased to "1") after power up and the PPBs retain their previous state as they are non-volatile. The default DYB state is cleared (erased to "1") with the sectors in the unprotected state. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is necessary. The DYB Set or Clear command for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again will lock the PPBs, and the device operates normally again. Note: to achieve the best protection, it's recommended to execute the PPB Lock Bit Set command early in the boot code, and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC = VIH. Table 5. DYB 1 0 1 0 1 0 1 0 PPB 1 1 0 0 1 1 0 0 Sector Protection Schemes PPB Lock 1 1 1 1 0 0 0 0 Sector State Sector Unprotected Sector Protected through DYB Sector Protected through PPB Sector Protected through PPB and DYB Sector Unprotected Sector Protected through DYB Sector Protected through PPB Sector Protected through PPB and DYB Table 5 contains all possible combinations of the DYB, PPB, and PPB Lock relating to the status of the sector. In summary, if the PPB is set (programmed to "0"), and the PPB Lock is set (programmed to "0"), the sector is protected and the protection can not be removed until the next power cycle clears (erase to "1") the PPB Lock Bit. Once the PPB Lock Bit is cleared (erased to "1"), the sector can be persistently locked or unlocked. Likewise, if both PPB Lock Bit or PPB is cleared (erased to "1") the sector can then be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program or erase command to a pro- 32 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information tected sector enables status polling and returns to read mode without having modified the contents of the protected sector. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. Password Sector Protection The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection Mode and the Password Sector Protection Mode: When the device is first powered up, or comes out of a reset cycle, the PPB Lock Bit is set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock Bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Lock Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock Bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock Bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 1 s delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands. The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode The Persistent Protection Bit Lock (PPB Lock Bit) is a volatile bit that reflects the state of the Password Mode Lock Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command to enter the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET# or taking the device through a power-on reset, resets the PPB Lock Bit to a "1". If the Password Mode Lock Bit is not set (device is operating in the default Persistent Protection Mode). The Password Unlock command is ignored in Persistent Sector Protection Mode. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 33 Advance Information Lock Register The Lock Register consists of 4 bits. The Customer SecSi Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, Password Protection Mode Lock Bit is DQ2, and Persistent Sector Protection OTP Bit is DQ3. Each of these bits are non-volatile. DQ15-DQ4 are reserved and will be 1's. Table 6. DQ15-3 1's DQ2 Lock Register DQ1 DQ0 Password Protection Persistent Protection Customer SecSi Mode Lock Bit Mode Lock Bit Sector Protection Bit Hardware Data Protection Mode The device offers two types of data protection at the sector level: When WP# is at VIL, the four outermost sectors are locked (device specific). When ACC is at VIL, all sectors are locked. The write protect pin (WP#) adds a final level of hardware program and erase protection to the outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of outermost sectors in a dual-bootconfigured device. When this pin is low it is not possible to change the contents of these outermost sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the "outermost" boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. 34 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in "DC Characteristics" represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in "DC Characteristics" represents the automatic sleep mode current specification. RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current will be greater. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 35 Advance Information RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the device requires a time of tRP+tRP (during Embedded Algorithms) before the device is ready to read data again. If RESET# is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tRP (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH. Refer to the "Hardware Reset (RESET#)" section for RESET# parameters and to Figure 20 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 words in length. All reads outside of the 256 word address range will return non-valid data. The Factory Indicator Bit (DQ7) is used to indicate whether or not the Factory SecSi Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer SecSi Sector is locked when shipped from the factory. The Factory SecSi bits are permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN and customer code once the product is shipped to the field. The Factory portion of the SecSi Sector is locked when shipped and the Customer SecSi Sector that is either locked or is lockable. The Factory SecSi Sector is always protected when shipped from the factory, and has the Factory Indicator Bit (DQ7) permanently set to a "1". The Customer SecSi Sector is typically shipped unprotected, allowing customers to utilize that sector in any manner they choose. The Customer Indicator Bit set to "0." Once the Customer SecSi Sector area is protected, the Customer Indicator Bit will be permanently set to "1." The system accesses the SecSi Sector through a command sequence (see the "Enter SecSiTM Sector/Exit SecSi Sector Command Sequence" section). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the memory array. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. While SecSi Sector access is enabled, Memory Array read access, program operations, and erase operations to all sectors other than SA0 are also available. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory Locked: Factor SecSi Sector Programmed and Protected At the Factory In a factory sector locked device, the Factory SecSi Sector is protected when the device is shipped from the factory. The Factory SecSi Sector cannot be modified in any way. The device is pre programmed with both a random number and a secure ESN. The Factory SecSi Sector is located at addresses 000000h-00007Fh. The device is available pre programmed with one of the following: 36 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information A random, secure ESN only within the Factor SecSi Sector Customer code within the Customer SecSi Sector through the SpansionTM programming service Both a random, secure ESN and customer code through the SpansionTM programming service. Table 7. Sector Customer Factory SecSiTM Sector Addresses Address Range 000080h-0000FFh 000000h-00007Fh Sector Size 128 words 128 words Customers may opt to have their code programmed by Spansion through the SpansionTM programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from Spansion's factory with the Factory SecSi Sector and Customer SecSi Sector permanently locked. Contact your local representative for details on using SpansionTM programming services. Customer SecSi Sector If the security feature is not required, the Customer SecSi Sector can be treated as an additional Flash memory space. The Customer SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer SecSi Sector, but reading in Banks 1 through 15 is available. The Customer SecSi Sector is located at addresses 000080h-0000FFh. The Customer SecSi Sector area can be protected by writing the SecSi Sector Protection Bit Lock command sequence. Once the Customer SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The Customer SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the Customer SecSi Sector area and none of the bits in the Customer SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bit The Customer SecSi Sector Protection Bit prevents programming of the Customer SecSi Sector memory area. Once set, the Customer SecSi Sector memory area contents are non-modifiable. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 8 June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 37 Advance Information through Table 11 within that bank. All reads outside of the CFI address range, within the bank, will return non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 8 through Table 11. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100. Please contact your sales office for copies of these documents. Table 8. Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h CFI Query Identification String Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 9. Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0005h 0009h 0008h 0000h 0003h 0001h 0003h 0000h System Interface String Description VCC Min. (write/erase) DQ7-DQ4: volt, DQ3-DQ0: 100 millivolt VCC Max. (write/erase) DQ7-DQ4: volt, DQ3-DQ0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s (Note ) Typical timeout for Min. size buffer write 2N s (00h = not supported) (Note ) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical (Note ) Max. timeout for buffer write 2N times typical (Note ) Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Not supported due to page programming requirement 38 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Table 10. Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0019h (WS256N) 0001h 0000h 0005h 0000h 0003h 0003h 0000h 0080h 0000h 00FDh (WS256N) 0000h 0000h 0002h 0003h 0000h 0080h 0000h 0000h 0000h 0000h 0000h Device Geometry Definition Description Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Table 11. Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0034h 0010h Primary Vendor-Specific Extended Query Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0011 = 0.13 m Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 08 = Advanced Sector Protection Simultaneous Operation Number of Sectors in all banks except boot bank 46h 47h 48h 49h 4Ah 0002h 0001h 0000h 0008h 00DFh (WS256N) June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 39 Advance Information Table 11. Addresses 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h Data 0001h 0000h 0085h 0095h 0001h 0001h 0001h 0007h 0014h 0014h 0005h 0005h 0010h Primary Vendor-Specific Extended Query (Continued) Description Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, DQ7-DQ4: Volt, DQ3-DQ0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, DQ7-DQ4: Volt, DQ3-DQ0: 100 mV Top/Bottom Boot Sector Flag 0001h = Dual Boot Device Program Suspend. 00h = not supported Unlock Bypass 00 = Not Supported, 01=Supported SecSi Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns Erase Suspend Time-out Maximum 2N ns Program Suspend Time-out Maximum 2N ns Bank Organization: X = Number of banks Bank 0 Region Information. X = Number of sectors in bank Bank 1 Region Information. X = Number of sectors in bank Bank 2 Region Information. X = Number of sectors in bank Bank 3 Region Information. X = Number of sectors in bank Bank 4 Region Information. X = Number of sectors in bank Bank 5 Region Information. X = Number of sectors in bank Bank 6 Region Information. X = Number of sectors in bank Bank 7 Region Information. X = Number of sectors in bank Bank 8 Region Information. X = Number of sectors in bank Bank 9 Region Information. X = Number of sectors in bank Bank 10 Region Information. X = Number of sectors in bank Bank 11 Region Information. X = Number of sectors in bank Bank 12 Region Information. X = Number of sectors in bank Bank 13 Region Information. X = Number of sectors in bank Bank 14 Region Information. X = Number of sectors in bank Bank 15 Region Information. X = Number of sectors in bank 0013h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0010h (WS256N) 0013h (WS256N) 40 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Table 12. Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 Bank 0 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 Bank 1 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Sector Address / Memory Address Map for the WS256N Sector Size 16 Kwords 16 Kwords 16 Kwords 16 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords A23-A14 0000000000 0000000001 0000000010 0000000011 00000001XX 00000010XX 00000011XX 00000100XX 00000101XX 00000110XX 00000111XX 00001000XX 00001001XX 00001010XX 00001011XX 00001100XX 00001101XX 00001110XX 00001111XX 00010000XX 00010001XX 00010010XX 00010011XX 00010100XX 00010101XX 00010110XX 00010111XX 00011000XX 00011001XX 00011010XX 00011011XX 00011100XX 00011101XX 00011110XX 00011111XX (x16) Address Range 000000h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 41 Advance Information Table 12. Bank Sector Address / Memory Address Map for the WS256N (Continued) Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords A23-A14 00100000XX 00100001XX 00100010XX 00100011XX 00100100XX 00100101XX 00100110XX 00100111XX 00101000XX 00101001XX 00101010XX 00101011XX 00101100XX 00101101XX 00101110XX 00101111XX 00110000XX 00110001XX 00110010XX 00110011XX 00110100XX 00110101XX 00110110XX 00110111XX 00111000XX 00111001XX 00111010XX 00111011XX 00111100XX 00111101XX 00111110XX 00111111XX (x16) Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh Sector SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 Bank 2 Bank 3 42 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Table 12. Bank Sector Address / Memory Address Map for the WS256N (Continued) Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords A23-A14 01000000XX 01000001XX 01000010XX 01000011XX 01000100XX 01000101XX 01000110XX 01000111XX 01001000XX 01001001XX 01001010XX 01001011XX 01001100XX 01001101XX 01001110XX 01001111XX 01010000XX 01010001XX 01010010XX 01010011XX 01010100XX 01010101XX 01010110XX 01010111XX 01011000XX 01011001XX 01011010XX 01011011XX 01011100XX 01011101XX 01011110XX 01011111XX (x16) Address Range 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh Sector SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 Bank 4 Bank 5 June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 43 Advance Information Table 12. Bank Sector Address / Memory Address Map for the WS256N (Continued) Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords A23-A14 01100000XX 01100001XX 01100010XX 01100011XX 01100100XX 01100101XX 01100110XX 01100111XX 01101000XX 01101001XX 01101010XX 01101011XX 01101100XX 01101101XX 01101110XX 01101111XX 01110000XX 01110001XX 01110010XX 01110011XX 01110100XX 01110101XX 01110110XX 01110111XX 01111000XX 01111001XX 01111010XX 01111011XX 01111100XX 01111101XX 01111110XX 01111111XX (x16) Address Range 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh Sector SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 Bank 6 Bank 7 44 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Table 12. Bank Sector Address / Memory Address Map for the WS256N (Continued) Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords A23-A14 10000000XX 10000001XX 10000010XX 10000011XX 10000100XX 10000101XX 10000110XX 10000111XX 10001000XX 10001001XX 10001010XX 10001011XX 10001100XX 10001101XX 10001110XX 10001111XX 10010000XX 10010001XX 10010010XX 10010011XX 10010100XX 10010101XX 10010110XX 10010111XX 10011000XX 10011001XX 10011010XX 10011011XX 10011100XX 10011101XX 10011110XX 10011111XX (x16) Address Range 800000h-80FFFFh 810000h-81FFFFh 820000h-82FFFFh 830000h-83FFFFh 840000h-84FFFFh 850000h-85FFFFh 860000h-86FFFFh 870000h-87FFFFh 880000h-88FFFFh 890000h-89FFFFh 8A0000h-8AFFFFh 8B0000h-8BFFFFh 8C0000h-8CFFFFh 8D0000h-8DFFFFh 8E0000h-8EFFFFh 8F0000h-8FFFFFh 900000h-90FFFFh 910000h-91FFFFh 920000h-92FFFFh 930000h-93FFFFh 940000h-94FFFFh 950000h-95FFFFh 960000h-96FFFFh 970000h-97FFFFh 980000h-98FFFFh 990000h-99FFFFh 9A0000h-9AFFFFh 9B0000h-9BFFFFh 9C0000h-9CFFFFh 9D0000h-9DFFFFh 9E0000h-9EFFFFh 9F0000h-9FFFFFh Sector SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 Bank 8 Bank 9 June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 45 Advance Information Table 12. Bank Sector Address / Memory Address Map for the WS256N (Continued) Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords A23-A14 10100000XX 10100001XX 10100010XX 10100011XX 10100100XX 10100101XX 10100110XX 10100111XX 10101000XX 10101001XX 10101010XX 10101011XX 10101100XX 10101101XX 10101110XX 10101111XX 10110000XX 10110001XX 10110010XX 10110011XX 10110100XX 10110101XX 10110110XX 10110111XX 10111000XX 10111001XX 10111010XX 10111011XX 10111100XX 10111101XX 10111110XX 10111111XX (x16) Address Range A00000h-A0FFFFh A10000h-A1FFFFh A20000h-A2FFFFh A30000h-A3FFFFh A40000h-A4FFFFh A50000h-A5FFFFh A60000h-A6FFFFh A70000h-A7FFFFh A80000h-A8FFFFh A90000h-A9FFFFh AA0000h-AAFFFFh AB0000h-ABFFFFh AC0000h-ACFFFFh AD0000h-ADFFFFh AE0000h-AEFFFFh AF0000h-AFFFFFh B00000h-B0FFFFh B10000h-B1FFFFh B20000h-B2FFFFh B30000h-B3FFFFh B40000h-B4FFFFh B50000h-B5FFFFh B60000h-B6FFFFh B70000h-B7FFFFh B80000h-B8FFFFh B90000h-B9FFFFh BA0000h-BAFFFFh BB0000h-BBFFFFh BC0000h-BCFFFFh BD0000h-BDFFFFh BE0000h-BEFFFFh BF0000h-BFFFFFh Sector SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 Bank 10 Bank 11 46 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Table 12. Bank Sector Address / Memory Address Map for the WS256N (Continued) Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords A23-A14 11000000XX 11000001XX 11000010XX 11000011XX 11000100XX 11000101XX 11000110XX 11000111XX 11001000XX 11001001XX 11001010XX 11001011XX 11001100XX 11001101XX 11001110XX 11001111XX 11010000XX 11010001XX 11010010XX 11010011XX 11010100XX 11010101XX 11010110XX 11010111XX 11011000XX 11011001XX 11011010XX 11011011XX 11011100XX 11011101XX 11011110XX 11011111XX (x16) Address Range C00000h-C0FFFFh C10000h-C1FFFFh C20000h-C2FFFFh C30000h-C3FFFFh C40000h-C4FFFFh C50000h-C5FFFFh C60000h-C6FFFFh C70000h-C7FFFFh C80000h-C8FFFFh C90000h-C9FFFFh CA0000h-CAFFFFh CB0000h-CBFFFFh CC0000h-CCFFFFh CD0000h-CDFFFFh CE0000h-CEFFFFh CF0000h-CFFFFFh D00000h-D0FFFFh D10000h-D1FFFFh D20000h-D2FFFFh D30000h-D3FFFFh D40000h-D4FFFFh D50000h-D5FFFFh D60000h-D6FFFFh D70000h-D7FFFFh D80000h-D8FFFFh D90000h-D9FFFFh DA0000h-DAFFFFh DB0000h-DBFFFFh DC0000h-DCFFFFh DD0000h-DDFFFFh DE0000h-DEFFFFh DF0000h-DFFFFFh Sector SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 Bank 12 Bank 13 June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 47 Advance Information Table 12. Bank Sector Address / Memory Address Map for the WS256N (Continued) Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 16 Kwords 16 Kwords 16 Kwords 16 Kwords A23-A14 11100000XX 11100001XX 11100010XX 11100011XX 11100100XX 11100101XX 11100110XX 11100111XX 11101000XX 11101001XX 11101010XX 11101011XX 11101100XX 11101101XX 11101110XX 11101111XX 11110000XX 11110001XX 11110010XX 11110011XX 11110100XX 11110101XX 11110110XX 11110111XX 11111000XX 11111001XX 11111010XX 11111011XX 11111100XX 11111101XX 11111110XX 1111111100 1111111101 1111111110 1111111111 (x16) Address Range E00000h-E0FFFFh E10000h-E1FFFFh E20000h-E2FFFFh E30000h-E3FFFFh E40000h-E4FFFFh E50000h-E5FFFFh E60000h-E6FFFFh E70000h-E7FFFFh E80000h-E8FFFFh E90000h-E9FFFFh EA0000h-EAFFFFh EB0000h-EBFFFFh EC0000h-ECFFFFh ED0000h-EDFFFFh EE0000h-EEFFFFh EF0000h-EFFFFFh F00000h-F0FFFFh F10000h-F1FFFFh F20000h-F2FFFFh F30000h-F3FFFFh F40000h-F4FFFFh F50000h-F5FFFFh F60000h-F6FFFFh F70000h-F7FFFFh F80000h-F8FFFFh F90000h-F9FFFFh FA0000h-FAFFFFh FB0000h-FBFFFFh FC0000h-FCFFFFh FD0000h-FDFFFFh FE0000h-FEFFFFh FF0000h-FF3FFFh FF4000h-FF7FFFh FF8000h-FFBFFFh FFC000h-FFFFFFh Sector SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 Bank 14 Bank 15 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 48 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The "Command Definition Summary" section defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. Refer to "AC Characteristics--Synchronous" and "AC Characteristics--Asynchronous" for timing diagrams. Reading Array Data The device is automatically set to reading asynchronous array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. See the "Erase Suspend/Erase Resume Commands" section for more information. After the device accepts a Program Suspend command, the corresponding bank enters the program-suspend-read mode, after which the system can read data from any non-program-suspended sector within the same bank. See the "Program Suspend/Program Resume Commands" section for more information. The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the "Reset Command" section for more information. If DQ1 goes high during Write Buffer Programming, the system must issue the Write Buffer Abort Reset command. See also "Requirements for Asynchronous Read Operation (Non-Burst)" section and "Requirements for Synchronous (Burst) Read Operation" section for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figure 13, Figure 14, and Figure 18 show the timings. Set Configuration Register Command Sequence The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active (see Figure 16 for details). The configuration register must be set before the device will enter burst mode. On power up or reset, the device is set in asynchronous read mode and the configuration register is reset. The configuration register is not reset after deasserting CE#. The configuration register is loaded with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be D0h and address bits should be 555h. During the fourth cycle, the configuration code should be entered onto the data bus with the address bus set to address 000h. Once the data has been programmed into the configuration register, a software reset command is required to set the device into the correct state. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 49 Advance Information synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock). Read Configuration Register Command Sequence The configuration register can be read with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C6h and address bits should be 555h. During the fourth cycle, the configuration code should be read out of the data bus with the address bus set to address 000h. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (D15 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (D15 = 1) Synchronous Read Mode Only Figure 1. Synchronous/Asynchronous State Diagram Read Mode Setting This setting allows the system to enable or disable burst mode during system operations. Configuration Bit CR15 determines this setting: "1' for asynchronous mode, "0" for synchronous mode. Programmable Wait State Configuration The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Configuration Bit CR13-CR11 determine the setting (see Table 13). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. 50 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Table 13. CR13 0 0 0 0 1 1 1 1 Notes: Programmable Wait State Settings CR11 0 1 0 1 0 1 0 1 Total Initial Access Cycles 2 3 4 5 6 7 (default) Reserved Reserved CR12 0 0 1 1 0 0 1 1 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Programmable Wait State If the device is equipped with the handshaking option, the host system should set CR13-CR11 to 010 for a clock frequency of 54 MHz or to 011 for a clock frequency of 66 MHz for the system/device to execute at maximum speed. Table 14 describes the typical number of clock cycles (wait states) for various conditions. Boundary Crossing Latency If the device is operating above 66 MHz, an additional wait state must be inserted to account for boundary crossing latency. This is done by setting CR14 to a `1' (default). If the device is operating at or below 66 MHz, the additional wait state for boundary crossing is not needed. Therefore the CR14 can be changed to a `0' to remove boundary crossing latency. Set Internal Clock Frequency The device switches at the full frequency of the external clock up to 66 MHz when CR9 is set to a `1' (default). Table 14. Wait States for Handshaking Typical No. of Clock Cycles after AVD# Low Conditions at Address Initial address (VIO = 1.8 V) 54 MHz 4 66 MHz 5 Handshaking For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. See the "Autoselect Command Sequence" section for more information. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 51 Advance Information Burst Sequence Only sequential burst is allowed in the device. CR7 defaults to a `1' and must always be set to a `1'. Burst Length Configuration The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear with or without wrap around modes. A continuous sequence (default) begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 15 shows the CR2-CR0 and settings for the four read modes. Table 15. Burst Length Configuration Address Bits Burst Modes Continuous 8-word linear 16-word linear 32-word linear CR2 0 0 0 1 CR1 0 1 1 0 CR0 0 0 1 0 Note: Upon power-up or hardware reset the default setting is continuous. Burst Wrap Around By default, the device will perform burst wrap around with CR3 set to a `1'. Changing the CR3 to a `0' disables burst wrap around. Burst Active Clock Edge Configuration By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock edge is active for all synchronous accesses. CR6 determines this setting; "1" for rising active (default), "0" for falling active. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. CR8 determines this setting; "1" for RDY active (default) with data, "0" for RDY active one clock cycle before valid data. In asynchronous mode, RDY is an open-drain output. RDY Polarity By default, the RDY pin will always indicate that the device is ready to handle a new transaction with CR10 set to a `1' when high. In this case, the RDY pin is active high. Changing the CR10 to a `0' sets the RDY pin to be active low. In this 52 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information case, the RDY pin will always indicate that the device is ready to handle a new transaction when low. Configuration Register Table 16 shows the address bits that determine the configuration register settings for various device functions. Table 16. CR BIt CR15 CR14 CR13 CR12 Programmable Wait State CR11 Function Set Device Read Mode Boundary Crossing Settings (Binary) Configuration Register 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) 0 = No extra boundary crossing latency 1 = With extra boundary crossing latency (default) 000 = Data is valid on the 2nd active CLK edge after addresses are latched 001 = Data is valid on the 3rd active CLK edge after addresses are latched 010 = Data is valid on the 4th active CLK edge after addresses are latched 011 = Data is valid on the 5th active CLK edge after addresses are latched 100 = Data is valid on the 6th active CLK edge after addresses are latched 101 = Data is valid on the 7th active CLK edge after addresses are latched (default) 110 = Reserved 111 = Reserved 0 = RDY signal is active low 1 = RDY signal is active high (default) 0 = Reserved for Future Use 1 = Internal clock switches at full frequency of the external clock (default) 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 0 = Reserved for Future Use 1 = Sequential Burst Order (default) 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) 000 = Continuous (default) 010 = 8-Word Linear Burst Burst Length 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes: Device will be in the default state upon power-up or hardware reset. CR10 CR9 CR8 CR7 CR6 CR3 CR2 CR1 CR0 RDY Polarity Set Internal Clock Frequency RDY Burst Sequence Clock Burst Wrap Around Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 53 Advance Information The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend and program-suspend-read mode if that bank was in Program Suspend). Note: If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command sequence to RESET the device to reading array data. The standard RESET command will not work. See Table 17 for details on this command sequence. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The "Command Definition Summary" section shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. Autoselect does not support simultaneous operations nor synchronous mode. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. Read commands to other banks will return data from the array. Writes to other banks is not allowed. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address. The device ID is read in three cycles. Table 17. Description Manufacturer ID Device ID, Word 1 Address Autoselect Addresses Read Data 0001h 227Eh (BA) + 00h (BA) + 01h 54 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Table 17. Description Device ID, Word 2 Device ID, Word 3 Address Autoselect Addresses Read Data 2230 (WS256N) 2200 DQ15 - DQ8 = 0 DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 -Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5 - Handshake Bit 1 = Reserved, 0 = Standard Handshake DQ4 & DQ3 - WP# Protection Boot Code 00 = WP# Protects both Top Boot and Bottom Boot Sectors, (BA) + 0Eh (BA) + 0Fh Indicator Bits (BA) + 03h 01 = Reserved, 10 = Reserved 11 = Reserved DQ2 = 0 DQ1 - DYB Power up state (DQ1 = Lock Register DQ4) 1 = Unlocked (user option) 0 = Locked (default) DQ0 - PPB Eraseability (DQ0 = Lock Register DQ3) 1 = Erase allowed 0 = Erase disabled The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend). Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The "Command Definition Summary" section shows the address and data requirements for both command sequences. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 55 Advance Information When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. Programming to the same word address multiple times without intervening erases is limited. For such application requirements, please contact your local Spansion representative. Any word cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Write Buffer Programming Command Sequence Write Buffer Programming Sequence allows for faster programming compared to the standard Program Command Sequence. Write Buffer Programming allows the system to write 32 words in one programming operation. See the "Write Buffer Programming Operation" section for the program command sequence. Table 18. Sequence Unlock Command 1 Unlock Command 2 Write Buffer Load Specify the Number of Program Locations Load 1st data word Load next data word ... Load last data word Write Buffer Program Confirm Device goes busy Status monitoring through DQ pins (Perform Data Bar Polling on the Last Loaded Address) Address 555 2AA Write Buffer Command Sequence Data 00AA 0055 0025h Word Count Program Data Program Data ... Program Data 0029h Number of locations to program minus 1 (must be 32 - 1 = 31) All addresses must be within write-buffer-page boundaries, but do not have to be loaded in any order Same as above Same as above Same as above This command must follow the last write buffer location loaded, or the operation will ABORT Comment Not required in the Unlock Bypass mode Same as above Starting Address Starting Address Starting Address Write Buffer Location ... Write Buffer Location Sector Address 56 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Write "Write to Buffer" command and Sector Address Write number of addresses to program minus 1 (WC = 31) and Sector Address Part of "Write to Buffer" Command Sequence Write first address/data Yes WC = 0 ? No Abort Write to Buffer Operation? No Write next address/data pair Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address WC = WC - 1 Write program buffer to flash sector address Read DQ15 - DQ0 at Last Loaded Address DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ15 - DQ0 with address = Last Loaded Address No Yes DQ7 = Data? No FAIL or ABORT Yes PASS Figure 2. Write Buffer Programming Operation Unlock Bypass Command Sequence The unlock bypass feature allows faster programming than the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command se- June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 57 Advance Information quence, resulting in faster total programming time. The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. The "Command Definition Summary" section shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the ACC input. When the system asserts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC input to accelerate the operation. Figure 3 illustrates the algorithm for the program operation. Refer to the Erase/ Program Operations table in "AC Characteristics--Asynchronous" for parameters, and Figure 21 for timing diagrams. START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See the "Command Definition Summary" section for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation or, in the unlock bypass mode, a four-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to 58 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The "Command Definition Summary" section shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to "Write Operation Status" for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles in length instead of six cycles. Figure 4 illustrates the algorithm for the erase operation. Refer to the "Erase/Program Operations @ VIO = 1.8 V" section for parameters and timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation or, in the unlock bypass mode, a fourcycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. The "Command Definition Summary" section shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 59 Advance Information DQ7 or DQ6/DQ2 in the erasing bank. Refer to "Write Operation Status" for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. Figure 4 illustrates the algorithm for the erase operation. Refer to the "Erase/Program Operations @ VIO = 1.8 V" section for parameters and timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 20 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the "Write Buffer Programming Operation" section and the "Autoselect Command Sequence" section for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. 60 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See the "Command Definition Summary" section for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation or a "Write to Buffer" programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within 20 s and updates the status bits. Addresses are "don't-cares" when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in Program Suspend mode. The device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system must write the Program Resume command (address bits are "don't care") to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 61 Advance Information Program Suspend command can be written after the device has resumed programming. Lock Register Command Set Definitions The Lock Register Command Set permits the user to program the SecSi Sector Protection Bit, Persistent Protection Mode Lock Bit, or Password Protection Mode Lock Bit one time. The Lock Command Set also allows for the reading of the SecSi Sector Protection Bit, Persistent Protection Mode Lock Bit, or Password Protection Mode Lock Bit. The Lock Register Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. Lock Register Program Command Lock Register Read Command Lock Register Exit Command Note that issuing the Lock Register Command Set Entry command disables reads and writes for Bank 0. Reads from other banks excluding Bank 0 are allowed. The Lock Register Command Set Exit command must be issued after the execution of the commands to reset the device to read mode. Otherwise the device will hang. For either the SecSi Sector to be locked, or the device to be permanently set to the Persistent Protection Mode or the Password Protection Mode, the sequence of a Lock Register Command Set Exit command, must be initiated after issuing the SecSi Protection Bit Program, Persistent Protection Mode Locking Bit Program, or the Password Protection Mode Locking Bit Program commands. Note that if the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are programmed at the same time, neither will be programmed. Note that issuing the Lock Register Command Set Exit command re-enables reads and writes for Bank 0. Password Protection Command Set Definitions The Password Protection Command Set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. The Password Protection Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. Password Program Command Password Read Command Password Unlock Command Note that issuing the Password Protection Command Set Entry command disables reads and writes for Bank 0. Reads and Writes for other banks excluding Bank 0 are allowed. The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. There is no special addressing order required for programming the password. 62 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program AlgorithmTM with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64bit password combinations are valid as a password. The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 1 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long. A1 and A0 are used for matching. Writing the Password Unlock command does not need to be address order specific. An example sequence is starting with the lower address A1-A0= 00, followed by A1-A0= 01, A1-A0= 10, and A1-A0= 11. Approximately 1 Sec is required for unlocking the device after the valid 64-bit password is given to the device. It is the responsibility of the microprocessor to keep track of the 64-bit password as it is entered with the Password Unlock command, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to re-lock the device into the Password Mode, the PPB Lock Bit Set command can be re-issued. The Password Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Otherwise the device will hang. Note that issuing the Password Protection Command Set Exit command reenables reads and writes for Bank 0. Non-Volatile Sector Protection Command Set Definitions The Non-Volatile Sector Protection Command Set permits the user to program the Persistent Protection Bits (PPBs), erase all of the Persistent Protection Bits (PPBs), and read the logic state of the Persistent Protection Bits (PPBs). The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. PPB Program Command All PPB Erase Command PPB Status Read Command Note that issuing the Non-Volatile Sector Protection Command Set Entry command disables reads and writes for the bank selected. Reads within that June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 63 Advance Information bank, will return the PPB status for that sector. Writes within that bank, will set the PPB for that sector. Reads from other banks are allowed, writes are not allowed. All Reads must be performed using the Asynchronous mode. The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A23-A14 WS256N) are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program command will not execute and the command will time-out without programming the PPB. The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. The device will preprogram all PPBs prior to erasing when issuing the All PPB Erase command. Also note that the total number of PPB program/erase cycles has the same endurance as the flash memory array. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device. The Non-Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Non-Volatile Sector Protection Command Set Exit command re-enables reads and writes for Bank 0. Global Volatile Sector Protection Freeze Command Set The Global Volatile Sector Protection Freeze Command Set permits the user to set the PPB Lock Bit and reading the logic state of the PPB Lock Bit. The Volatile Sector Protection Freeze Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. PPB Lock Bit Set Command PPB Lock Bit Status Read Command Reads from all banks are allowed. The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear (for Persistent Sector Protection Mode) or the Password Unlock command is executed (for Password Sector Protection Mode). If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. The programming state of the PPB Lock Bit can be verified by executing a PPB Lock Bit Status Read Command to the device. The Global Volatile Sector Protection Freeze Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. 64 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Volatile Sector Protection Command Set The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the following commands to enable proper command execution. DYB Set Command DYB Clear Command DYB Status Read Command Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes for the bank selected with the command. Reads within that bank, will return the DYB status for that sector. Writes within that bank, will set the DYB for that sector. Reads for other banks excluding that bank are allowed, writes are not allowed. All Reads must be performed using the Asynchronous mode. The DYB Set/Clear command is used to set or clear a DYB for a given sector. The high order address bits (A23-A14 for the WS256N) are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. The programming state of the DYB for a given sector can be verified by writing a DYB Status Read Command to the device. The Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes for Bank 0. SecSi Sector Entry Command The SecSi Sector Entry Command allows the following commands to be executed Read from SecSi Sector Program to SecSi Sector Sector 0 is remapped from memory array to SecSi Sector array. Reads can be performed using the Asynchronous or Synchronous mode. Burst mode reads within SecSi Sector will wrap from address FFh back to address 00h. Reads outside of sector 0 will return memory array data. Continuous burst read past the maximum address is undefined. Simultaneous operations are allowed except for Bank 0. Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command has to be issued to exit SecSi Sector Mode. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 65 Advance Information Command Definition Summary Bus Cycles (Notes 1-6) First Addr RA XXX 555 555 Data RD F0 AA AA 2AA 2AA 55 55 (BA) 555 (BA) 555 (BA) 555 555 PA 90 90 (BA) X00 (BA) X01 (BA) X03 PA PA 0001 227E (Note 12) Data WC PA PD WBL PD (BA) X0E (Note 10) (BA) X0F 2200 Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data Command Sequence (Note 1) Asynchronous Read (Note 7) Reset (Note 8) Autoselect (Note 9) Manufacturer ID Device ID (Note 10) Indicator Bits Cycles 1 1 4 6 4 4 6 1 3 6 6 1 1 4 4 1 3 2 2 2 1 2 3 6 1 4 3 2 1 2 555 555 555 SA 555 555 555 BA BA 555 555 (BA) 555 555 XX XX XX XX XX 555 555 00 555 555 XX 77 (Note 25) XX AA AA AA 29 AA AA AA B0 30 AA AA 98 AA A0 80 80 98 90 AA AA data AA AA A0 data 90 2AA 2AA 2AA 55 55 55 90 A0 25 Program Write to Buffer (Note 18) Program Buffer to Flash Write to Buffer Abort Reset (Note 22) Chip Erase Sector Erase Erase/Program Suspend (Note 15) Erase/Program Resume (Note 16) Set Configuration Register Read Configuration Register CFI Query (Note 18) Unlock Bypass Entry (Note 24) Unlock Bypass Program (Notes 13, 14) Unlock Bypass Sector Erase (Notes 13, 14) Unlock Bypass Erase (Notes 13, 14) Unlock Bypass CFI (Notes 13, 14) Unlock Bypass Reset SecSi Sector SecSi Sector Entry (Note 23) SecSi Sector Program SecSi Sector Read SecSi Sector Exit (Note 26) Lock Register Command Set Entry (Note 23) Lock Register Bits Program (Note 25) Lock Register Bits Read (Note 25) Lock Register Command Set Exit (Note 26) 2AA 2AA 2AA 55 55 55 555 555 555 F0 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 2AA 2AA 55 55 555 555 D0 C6 X00 X00 CR CR 2AA PA SA XXX 55 PD 30 10 555 20 Unlock Bypass Mode XXX 2AA 2AA 2AA 2AA 77 (Note 25) 00 55 55 55 55 data 555 SA 555 555 88 25 90 40 SA XX WC 00 PA PD WBL PD SecSi Sector Command Definitions Lock Register Command Set Definitions Lock XX 00 66 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information (Continued) Command Sequence (Note 1) Cycles Bus Cycles (Notes 1-6) First Addr Data Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data Password Protection Command Set Definitions Password Protection Command Set Entry (Note 23) 3 555 XX XX Password Password Program* 2 XX XX Password Read** Password Unlock*** Password Protection Command Set Exit (Note 26) Non-Volatile Sector Protection Command Set Entry (Note 23) PPB PPB Program All PPB Erase (Note 20) PPB Status Read Non-Volatile Sector Protection Command Set Exit (Note 26) Global Volatile Sector Protection Freeze Command Set Entry (Note 23) PPB Lock Bit Set PPB Lock Bit Status Read Global Volatile Sector Protection Freeze Command Set Exit (Note 26) 4 7 2 00 00 XX A0 A0 PWD 0 25 90 02 03 01 00 XX AA A0 A0 2AA 00 01 55 PWD 0 PWD 1 PWD 2 PWD 3 PWD 1 03 00 02 00 PWD 2 PWD 0 03 01 PWD 3 PWD 1 02 PWD 2 03 PWD 3 00 29 555 60 Non-Volatile Sector Protection Command Set Definitions 3 2 2 1 2 555 XX XX (BA) SA XX AA A0 80 RD (0) 90 XX 00 2AA (BA) SA XX 55 00 30 (BA) 555 C0 Global Non-Volatile Sector Protection Freeze Command Set Definitions 3 2 1 2 555 XX XX XX AA A0 RD (0) 90 XX 00 2AA XX 55 00 555 50 * Only A7-A0 used during 2nd cycle ** Amax-A0 used during 1st, 2nd, 3rd, 4th cycle *** Only A7-A0 used during 3rd, 4th, 5th 6th cycle Volatile Sector Protection Command Set Definitions Volatile Sector Protection Command Set Entry (Note 23) DYB Set DYB DYB Clear DYB Status Read Volatile Sector Protection Command Set Exit (Note 26) 3 2 2 1 2 555 XX XX (BA) SA XX AA A0 A0 RD (0) 90 XX 00 2AA (BA) SA (BA) SA 55 00 01 (BA) 555 E0 June 28, 2004 S71WS512NE0BFWZZ_00_A1 PPB Lock Bit S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 67 Advance Information Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0]. PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to `0' for protection while PD(2), bit[2] must be left as `1'. PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to `0' for protection while PD(1), bit[1] must be left as `1'. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A23-A14 for the WS256N uniquely select any sector. Notes: 1. See Table 2 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0. 5. Unless otherwise noted, address bits A23-A12 for the WS256N are don't cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the "Autoselect Command Sequence" section 10. WS25N6 = 2230 11. The data is 0000h for an unlocked sector and 0001h for a locked sector 12. See the "Autoselect Command Sequence" section 13. The Unlock Bypass command sequence is required prior to this command sequence. 14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 16. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. BA = Address of the bank (A23, A22, A21, and A20 for the WS256N/ A22, A21, A20, that is being switched to autoselect mode, is in bypass mode, or is being erased. CR = Configuration Register data bits DQ15-DQ0. PWD3-PWD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 0, if unprotected, DQ1 = 1. RD(2) = DQ2 protection indicator bit. If protected, DQ2 = 0, if unprotected, DQ2 = 1. WBL = Write Buffer Location. Address must be within the same write buffer page as PA.] WC = Word Count. Number of write buffer locations to load minus 1. 18. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The number of cycles in the command sequence is 37 for full page programming (32 words). Less than 32 word programming is not recommended. 19. The entire four bus-cycle sequence must be entered for which portion of the password. 20. The ALL PPB ERASE command will pre-program all PPBs before erasure to prevent over-erasure of PPBs. 21. ACC must be at VHH during the entire operation of this command 22. Command sequence resets device for next command after write-to-buffer operation. 23. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 24. Write Buffer Programming can be initiated after Unlock Bypass Entry. 25. If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time, the command operation will abort and return the device to the default Persistent Sector Protection Mode during 2nd Bus cycle. Addresses will equal 00h on all future devices, but 77h for WS256N. 26. The Exit command must be issued to reset the device into read mode. Otherwise the device will hang. 68 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. Table 20 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. Table 20 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 24 in "AC Characteristics--Asynchronous" shows the Data# Polling timing diagram. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 69 Advance Information START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Figure 5. Data# Polling Algorithm RDY: Ready The RDY is a dedicated output, controlled by CE#, that indicates the number of clock cycles in the system should write before expecting valid data. When the device is configured in the Synchronous mode and RDY is at logic low, the system should wait 1 clock cycle before expecting the next word of data. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. The RDY output is at logic low if the frequency is greater than 66 MHZ during the initial access in burst mode and at the boundary crossing that occurs every 128 words beginning with address 7Fh. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading 70 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 ms after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 6, "DQ6: Toggle Bit I" section, Figure 25 (toggle bit timing diagram), and Table 19. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state. START Read Byte (DQ7-DQ0) Address =VA Read Byte (DQ7-DQ0) Address =VA Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice (DQ7-DQ0) Address = VA Toggle Bit = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command No Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 71 Advance Information DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 19 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 6, the "DQ6: Toggle Bit I" section, and Figure 25. Table 19. If device is programming, and the system reads at any address, DQ6 and DQ2 Indications then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. is not applicable. actively erasing, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at any address, erase suspended, programming in erase suspend Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7- DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other 72 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 6 for more details. DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See the "Sector Erase Command Sequence" section for more details. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 20 shows the status of DQ3 relative to the other status bits. DQ1: Write to Buffer Abort DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a `1'. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See the "Write Buffer Programming Operation" section for more details. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 73 Advance Information Table 20. Status Standard Mode Program Suspend Mode (Note 3) Embedded Program Algorithm Embedded Erase Algorithm Reading within Program Suspended Sector Reading within Non-Program Suspended Sector Erase-SuspendRead Erase Suspended Sector Non-Erase Suspended Sector Write Operation Status DQ7 (Note 2) DQ7# 0 INVALID (Not Allowed) DQ6 Toggle Toggle INVALID (Not Allowed) DQ5 (Note 1) 0 0 INVALID (Not Allowed) DQ3 N/A 1 INVALID (Not Allowed) DQ2 (Note 2) No toggle Toggle INVALID (Not Allowed) DQ1 (Note 4) 0 N/A INVALID (Not Allowed) Data 1 Data DQ7# DQ7# DQ7# DQ7# Data No toggle Data Toggle Toggle Toggle Toggle Data 0 Data 0 0 1 0 Data N/A Data N/A N/A N/A N/A Data Toggle Data N/A N/A N/A N/A Data N/A Data N/A 0 0 1 Erase Suspend Mode Erase-Suspend-Program Write to Buffer (Note 5) Notes: BUSY State Exceeded Timing Limits ABORT State 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. Data are invalid for addresses in a Program Suspended sector. 4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. 5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITEBUFFER ADDRESS location. 74 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Voltage with Respect to Ground: All Inputs and DQs except as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VIO + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +2.5 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +2.5 V ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +9.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Notes: 1. Minimum DC voltage on input or DQs is -0.5 V. During voltage transitions, inputs or DQs may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or DQs is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 9 3. 4. 20 ns +0.8 V -0.5 V -2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns 20 ns Figure 7. Maximum Negative Overshoot Waveform Figure 8. Maximum Positive Overshoot Waveform Operating Ranges Wireless (W) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Supply Voltages VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65 V to +1.95 V VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.35 V to +1.70 V Notes: Operating ranges define those limits between which the functionality of the device is guaranteed. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 75 Advance Information DC Characteristics CMOS Compatible Parameter ILI ILO Description Input Load Current Output Leakage Current (Note 7) Test Conditions (Note: 1 & 2) VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous IIO1 ICC1 VIO Non-active Output VCC Active Asynchronous Read Current (Note 3) OE# = VIH CE# = VIL, OE# = VIH, WE# = VIH CE# = VIL, OE# = VIH, ACC = VIH CE# = RESET# = VCC 0.2 V 10 MHz 5 MHz 1 MHz VACC VCC VACC VCC 54 MHz 66 MHz 54 MHz 66 MHz 54 MHz 66 MHz 54 MHz 66 MHz 36 40 32 36 28 32 24 28 20 30 15 3 1 <35 1 20 20 <50 20 VACC VCC -0.5 VIO - 0.4 VIO - 0.1 8.5 1.0 9.5 1.4 <30 <15 Min Typ Max 1 1 54 60 48 54 42 48 36 42 30 36 18 4 5 <52.5 5 30 30 <60 30 <20 <20 0.4 VIO + 0.4 0.1 V V V V Unit A A mA mA mA mA mA mA mA mA A mA mA mA A mA A A A mA A mA mA V ICCB VCC Active burst Read Current ICC2 ICC3 ICC4 ICC5 ICC6 IACC VIL VIH VOL VOH VHH VLKO VCC Active Write Current (Note 4) VCC Standby Current (Note 5) VCC Reset Current VCC Active Current (Read While Write) VCC Sleep Current Accelerated Program Current (Note 6) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH, ACC = VIH CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VACC = 9.5 V VIO = 1.8 V VIO = 1.8 V IOL = 100 A, VCC = VCC min = VIO IOH = -100 A, VCC = VCC min = VIO Note: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. VCC= VIO 3. The ICC current listed is typically less than 3 mA/MHz, with OE# at VIH. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 20ns. Typical sleep mode current is equal to ICC3. 6. Total current during accelerated programming is the sum of VACC and VCC currents. 7. CE# must be set high when measuring the RDY pin. 76 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Test Conditions Device Under Test CL Figure 9. Table 21. Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Test Specifications All Speed Options 30 3.0 @ 54, 66 MHz 0.0-VIO VIO/2 VIO/2 Unit pF ns V V V Switching Waveforms Table 22. WAVEFORM Key to Switching Waveforms OUTPUTS Steady Changing from H to L Changing from L to H INPUTS Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) All Inputs and Outputs VIO 0.0 V Input VIO/2 Measurement Level VIO/2 Output Figure 10. Input Waveforms and Measurement Levels June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 77 Advance Information VCC Power-up Parameter tVCS tVIOS Description VCC Setup Time VIO Setup Time Test Setup Min Min Speed 1 50 Unit ms s Note: 1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100s 2. VCC ramp rate <1V / 100s, a Hardware Reset will be required. tVC VCC tVIO VIO RESET# Figure 11. VCC Power-up Diagram Pin Capacitance Symbol CIN1 CIN2 Cout Parameter Input Capacitance Output Capacitance Control Capacitance Test Condition VIN=0 Vout=0 VIN=0 Typ 4.2 5.4 3.9 Max 5.0 8.5 4.7 Unit pF pF pF 78 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information AC Characteristics--Synchronous CLK Characterization Parameter fCLK tCLK tCH tCL tCR tCF Description CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Max Min Min 54 MHz 54 18.5 7.4 66 MHz 66 15.1 6.1 Unit MHz ns ns Max 3 3 ns tCLK tCH tCL CLK tCR tCF tCLK tCH tCL CLK DIVIDER tCR tCF Figure 12. CLK Characterization June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 79 Advance Information Synchronous/Burst Read @ VIO = 1.8 V Parameter JEDEC Standard tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRDYS tRACC tAAS tAAH tCAS tAVC tAVD tCKA tCKZ tOES tRCC Notes: Description Latency Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (Note 1) Address Hold Time from CLK (Note 1) Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High Z Output Enable to High Z CE# Setup Time to CLK RDY Setup Time to CLK Ready Access Time from CLK Address Setup Time to AVD# (Note 1) Address Hold Time to AVD# (Note 1) CE# Setup Time to AVD# AVD# Low to CLK AVD# Pulse CLK to access resume CLK to High Z Output Enable Setup Time Read cycle for continuous suspend Max Max Min Min Min Max Max Max Max Min Min Max Min Min Min Min Min Max Max Min Max 54 MHz 69 13.5 5 7 4 13.5 13.5 10 10 5 5 13.5 5 7 0 5 12 13.5 10 5 1 66 MHz Unit ns 11.2 4 6 3 11.2 11.2 8 8 4 4 11.2 4 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 10 11.2 8 4 ns ns ns ns ns ms 1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. 2. Clock Divider option 80 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Timing Diagrams 5 cycles for initial access shown. tCES CE# 1 CLK tAVC AVD# tACS Addresses Aa tACH Data (n) tIACC Da Da + 1 tBDH OE# Hi-Z RDY (n) tCR tRDYS Hi-Z Da Hi-Z RDY (n + 1) Da + 1 Da + 2 Da + 2 Da + n Hi-Z tOE tRACC Hi-Z Da + 2 Da + 3 Da + n tOEZ tBACC Hi-Z tAVD 2 3 4 5 6 7 18.5 ns typ. (54 MHz) tCEZ Data (n + 1) Data (n + 2) Da Hi-Z RDY (n + 2) Da + 1 Da + 1 Da + 1 Da + n Hi-Z Hi-Z Data (n + 3) Da Hi-Z RDY (n + 3) Da Da Da Da + n Hi-Z Hi-Z Notes: 1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two cycles to seven cycles. 2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode. Figure 13. CLK Synchronous Burst Mode Read (rising active CLK) June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 81 Advance Information tCAS CE# 1 CLK tAVC AVD# tAAS Addresses Aa tAAH Data tAVD 7 cycles for initial access shown. 2 3 4 5 6 7 tCEZ tBACC Hi-Z tIACC tACC Da Da + 1 tBDH Da + n tOEZ OE# tCR Hi-Z RDY tRDYS tOE tRACC Hi-Z Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode. Figure 14. Synchronous Burst Mode Read tCES CE# 1 CLK tAVC AVD# tACS Addresses AC tACH Data tAVD 7 2 cycles for initial access shown. 3 4 5 6 7 tBACC tIACC DC DD tBDH DE DF D8 DB OE# tCR Hi-Z RDY tRDYS tOE tRACC tRACC Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in synchronous mode with wrap around. 4. DQ0-DQ7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (AC). Figure 15. Eight-word Linear Burst with Wrap Around 82 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information tCES CE# 1 CLK tAVC AVD# tACS Addresses AC tACH Data tAVD 7 2 cycles for initial access shown. 3 4 5 6 7 tBACC tIACC DC DD tBDH DE DF D10 D13 OE# tCR Hi-Z RDY tRDYS tOE tRACC tRACC Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at "address + 1", "address + 2", or "address + 3", additional clock delay cycles are inserted, and are indicated by RDY. 3. The device is in asynchronous mode with out wrap around. 4. DQ-DQ7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range (AC). Figure 16. Eight-word Linear Burst without Wrap Around tCES CE# 1 CLK tAVC AVD# tACS Addresses Aa tACH Data tAVD 6 2 wait cycles for initial access shown. 3 4 5 6 tCEZ tBACC Hi-Z tIACC tRACC Da Da+1 tBDH Da+2 Da+3 Da + n tOEZ OE# tCR Hi-Z RDY tOE Hi-Z tRDYS Notes: 1. Figure assumes 6 wait states for initial access and synchronous read. 2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one cycle before valid data. Figure 17. Linear Burst with RDY Set One Cycle Before Data June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 83 Advance Information AC Characteristics--Asynchronous Asynchronous Mode Read @ Parameter JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Notes: VIOpS = 1.8 V Description Access Time from CE# Low Asynchronous Access Time (Note 1) AVD# Low Time Address Setup Time to Rising Edge of AVD# Address Hold Time from Rising Edge of AVD# Output Enable to Output Valid Output Enable Hold Time Read Toggle and Data# Polling Max Max Min Min Min Max Min Min Max Min 54 MHz 70 70 12 5 7 13.5 0 10 10 0 66 MHz 70 70 10 4 6 11.2 Unit ns ns ns ns ns ns ns 8 8 ns ns ns Output Enable to High Z (Note 2) CE# Setup Time to AVD# 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. Timing Diagrams CE# OE# tOEH WE# Data tCE tO tOEZ Valid RD tACC Addresses tCAS AVD# tAVDP tAAVDS RA tAAVDH Note: RA = Read Address, RD = Read Data. Figure 18. Asynchronous Mode Read with Latched Addresses 84 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information CE# OE# tOEH WE# Data tACC Addresses RA tCE tO tOEZ Valid RD AVD# Note: RA = Read Address, RD = Read Data. Figure 19. Asynchronous Mode Read Hardware Reset (RESET#) Parameter JEDEC Std tRP Description RESET# Pulse Width Reset High Time Before Read (During Embedded Algorithms) to Read Mode (See Note) Reset High Time Before Read (NOT During Embedded Algorithms) to Read Mode (See Note) Min All Speed Options 1 Unit ms tRH Min 30 s Note: Not 100% tested. CE#, OE# tRH RESET# tRP Figure 20. Reset Timings June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 85 Advance Information Erase/Program Operations @ VIO = 1.8 V Parameter JEDEC tAVAV tAVWL tWLAX Standard tWC tAS tAH tAVDP tDVWH tWHDX tGHWL tWHEH tWLWH tWHWL tWHWH1 tWHWH1 tWHWH2 tDS tDH tGHWL tCAS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tVID tVIDS tVCS tELWL tCS tAVSW tAVHW tAVSC tAVHC tCSW Notes: Description Write Cycle Time (Note 1) Address Setup Time (Notes 2, 3) Address Hold Time (Notes 2, 3) AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 4) Accelerated Programming Operation (Note 4) Sector Erase Operation (Notes 4, 5) Chip Erase Operation (Notes 4, 5) VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# AVD# Setup Time to CLK AVD# Hold Time to CLK Clock Setup Time to WE# Synchronous Asynchronous Synchronous Asynchronous Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min Min Min Min Min Min Min 54 MHz 70 5 66 MHz 70 4 0 6 20 10 20 0 0 0 0 Unit ns ns 7 12 45 ns ns ns ns ns ns ns 30 20 0 <9.4 <4 0.4 25 ns ns ns s s sec ns s s <104 (WS256N) 500 1 50 5 5 5 5 5 5 4 4 4 4 4 ns ns ns ns ns ns 1. Not 100% tested. 2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the active edge of CLK or rising edge of AVD#. 4. See the "Erase and Programming Performance" section for more information. 5. Does not include the preprogramming time. 86 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Program Command Sequence (last two cycles) Read Status Data VIH CLK VIL tAVD AVD tAS tA Addresses 555h PA VA VA tAVS tAVH Data tCA CE# A0h tDS tD PD In Progress Complete OE# tW WE# tC tWHWH1 tCS tWC tVC VCC tWPH Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A23-A14 for the WS256N are don't care during command sequence unlock cycles. 4. CLK can be either VIL or VIH. 5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register. Figure 21. Asynchronous Program Operation Timings: WE# Latched Addresses June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 87 Advance Information Program Command Sequence (last two cycles) tAVCH CLK tAS tAH tAVSC AVD tAVDP Addresses 555h PA VA Read Status Data VA Data tCA CE# A0h PD tDS tD In Progress Complete OE# tCSW tWP tC WE# tWHWH1 tWPH tWC tVC VCC Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A23-A14 for the WS256N are don't care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 22. Synchronous Program Operation Timings: CLK Latched Addresses CE# AVD# WE# Addresses Data OE# ACC VID VIL or VIH Don't Care tVIDS tVID A0h PA Don't Care PD Don't Care 1 ms Note: Use setup and hold times from conventional program operation. Figure 23. Accelerated Unlock Bypass Programming Timing 88 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA High tOE tOEZ tCEZ Data Status Status High Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. Figure 24. Data# Polling Timings (During Embedded Algorithm) AVD# tCE CE# tCH OE# tOEH WE# tACC Addresses VA VA High tOE tOEZ tCEZ Data Status Status High Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. Figure 25. Toggle Bit Timings (During Embedded Algorithm) June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 89 Advance Information CE# CLK AVD# Addresses VA VA OE# tIACC Data Status Data tIACC Status Data RDY Notes: 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. RDY is active with data (DQ8 = 0 in the Configuration Register). When DQ8 = 1 in the Configuration Register, RDY is active one clock cycle before data. Figure 26. Synchronous Data Polling Timings/Toggle Bit Timings Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6 Figure 27. DQ2 vs. DQ6 90 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. C124 CLK Address (hex) AVD# 7C (stays high) C125 C126 C127 C127 C128 C129 C130 C131 7D 7E 7F 7F 80 81 82 83 tRACC RDY(1) tRACC RDY(2) latency latency tRACC tRACC Data D124 D125 D126 D127 D128 D129 D130 OE#, CE# (stays low) Notes: 1. RDY active with data (DQ8 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (DQ8 = 1 in the Configuration Register). 3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. 4. Figure shows the device not crossing a bank in the process of performing an erase or program. 5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (DQ14) in the Configuration Register is set to 0 Figure 28. Latency with Boundary Crossing when Frequency > 66 MHz Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. C124 CLK Address (hex) AVD# 7C (stays high) C125 C126 C127 C127 7D 7E 7F 7F tRACC RDY(1) tRACC RDY(2) latency latency tRACC tRACC Data D124 D125 D126 D127 Read Status OE#, CE# (stays low) Notes: 1. RDY active with data (DQ8 = 0 in the Configuration Register). 2. 3. 4. 5. RDY active one clock cycle before data (DQ8 = 1 in the Configuration Register). Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a bank in the process of performing an erase or program. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (DQ14) in the Configuration Register is set to 0 Figure 29. June 28, 2004 S71WS512NE0BFWZZ_00_A1 Latency with Boundary Crossing into Program/Erase Bank 91 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) Advance Information Data D0 D1 AVD# Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following addresses being latched OE# 1 CLK 0 1 2 3 4 5 6 7 2 3 4 5 number of clock cycles programmed Wait State Configuration Register Setup: DQ13, DQ12, DQ11 = "111" Reserved DQ13, DQ12, DQ11 = "110" Reserved DQ13, DQ12, DQ11 = "101" 5 programmed, 7 total DQ13, DQ12, DQ11 = "100" 4 programmed, 6 total DQ13, DQ12, DQ11 = "011" 3 programmed, 5 total DQ13, DQ12, DQ11 = "010" 2 programmed, 4 total DQ13, DQ12, DQ11 = "001" 1 programmed, 3 total DQ13, DQ12, DQ11 = "000" 0 programmed, 2 total Note: Figure assumes address DQ0 is not at an address boundary, active clock edge is rising, and wait state is set to "101". Figure 30. Last Cycle in Program or Sector Erase Command Sequence tWC Example of Wait States Insertion Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence tRC tRC tWC CE# OE# tOE tOEH WE# tWP tW tDS Data PD/30h tSR/ Addresses PA/SA tAS AVD# tAH RA RA 555h tD RD tACC tOEZ tOEH RD AAh tGHWL Note: Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information. Figure 31. 92 Back-to-Back Read/Write Cycle Timings S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 Advance Information Erase and Programming Performance Parameter Sector Erase Time 64 Kword 16 Kword VCC VCC VCC ACC VCC ACC VCC ACC VCC ACC Typ (Note 1) <0.4 <0.15 <104 (WS256N) <86.7(WS256N) <9.4 <4 <300 <64 <335.5 (WS256N) <145.9 (WS256N) Max (Note 2) 2.5 2 <208 (WS256N) <173.4 (WS256N) <18.8 <8 <600 <128 <671 (WS256N) <292 (WS256N) <20 <20 Unit s Comments Chip Erase Time Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time Chip Programming Time (Note 3) Erase Suspend/Erase Resume Program Suspend/Program Resume Notes: s Excludes 00h programming prior to erasure (Note 4) s s Excludes system level overhead (Note 5) s s s 1. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 10,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90C, VCC = 1.65 V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. Based upon single word programming, not page programming. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See the "Command Definition Summary" section for further information on command definitions. 6. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions. June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBitTM Flash Family For Multi-chip Products (MCP) 93 Preliminary 128Mb pSRAM (8M word x 16 bit) Pseudo SRAM with Page & Burst FEATURES Fast Access Cycle Time tCE =70ns max 8 words Page Read Access Capability tPAA =20ns max Burst Read/Write Access Capability tAC =11ns max Low Voltage Operating Condition VDD =+2.6 to +3.1V VDDQ =+1.65V to +1.95V Wide Operating Temperature TA =-30C to +85C Byte Control by UB# and LB# Low Power Consumption IDDA1 =35mA max IDDS1 =300 mA max Various Power Down mode Sleep, 16M-bit and 32M-bit Partial 94 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary FUNCTION TRUTH TABLE Asynchronous Operation (Page Mode) Mode Note CE2pS2 CE#1pS CLK ADV# WE# OE# LB# UB# A22-0 DQ0-7 DQ8-15 RDY Standby (Deselect) Output Disable Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) *1 H H X X X X X X X *3 *3 *3 *3 *3 *3 *3 *3 X H X H X X H H X X H L H L L/H H L H L X X *5 Valid Valid Valid Valid Valid Valid Valid Valid Valid X High-Z High-Z High-Z High-Z Output Valid Output Valid *6 Invalid Invalid Input Valid Input Valid High-Z High-Z High-Z High-Z Output Valid High-Z Output Valid *6 Invalid Input Valid Invalid Input Valid High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z H L L L L/H H H L L H Page Read No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down *2 L L X X X X X X X L *3 *3 X X H *4 X X Note: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance *1: Should not be kept this logic condition longer than 1ms. Please contact local FUJITSU representative for the relaxation of 1ms limitation. *2: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Partial Size. Refer to "Power Down" in FUNCTIONAL DESCRIPTION for the details. *3: "L" for address pass through and "H" for address latch on the rising edge of ADV#. *4: OE# can be VIL during Write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE#1 (refer to CE#1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied. (2) OE# stays VIL during Write cycle. *5: Can be either VIL or VIH but must be valid before Read or Write. *6: Output is either Valid or High-Z depending on the level of UB# and LB# input. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 95 Preliminary FUNCTION TRUTH TABLE (Continued) Synchronous Operation (Burst Mode) Mode Standby (Deselect) Start Address Latch Advance Burst Read to Next Address Burst Read Suspend Advance Burst Write to Next Address Burst Write Suspend Terminate Burst Read Terminate Burst Write Power Down *2 L X *1 *1 *1 H *1 *1 L Note CE2 CE#1 H CLK X *3 ADV# WE# X X *4 OE# X *4 LB# X UB# X A22-0 X Valid *7 DQ8-1 High-Z High-Z Output Valid High-Z *9 *8 DQ16-9 High-Z High-Z Output Valid High-Z Input Valid Input Invalid High-Z High-Z High-Z *10 *9 *8 WAIT# High-Z High-Z Output Valid High High High High-Z High-Z High-Z *12 *13 *12 *11 X X L *3 *3 H H *5 *6 *3 H *3 L X *6 X H *5 X Input Valid Input Invalid *10 H H X X X X X X H X X X X High-Z High-Z High-Z X Notes:L = VIL, H = VIH, X can be either VIL or VIH, = valid edge, = positive edge of Low pulse, High-Z = High Impedance *1: Should not be kept this logic condition longer than 4ms. Please contact local FUJITSU representative for the relaxation of 4ms limitation. *2: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Partial Size. Refer to "Power Down" in FUNCTIONAL DESCRIPTION for the details. *3: Valid clock edge shall be set on either positive or negative edge through CR Set. CLK must be started and stable prior to memory access. *4: Can be either VIL or VIH except for the case the both of OE# and WE# are VIL. It is prohibited to bring the both of OE# and WE# to VIL *5: When device is operating in "WE# Single Clock Pulse Control" mode, WE# is don't care once write operation is determined by WE# Low Pulse at the beginnig of write access together with address latching. Write suspend feature is not supported in "WE# Single Clock Pulse Control" mode *6: Can be either VIL or VIH but must be valid before Read or Write is determined. And once UB# and LB# inputs are determined, they must not be changed until the end of burst. *7: Once valid address is determined, input address must not be changed during ADV#=L. *8: If OE#=L, output is either Invalid or High-Z depending on the level of UB# and LB# input. If WE#=L, Input is Invalid. If OE#=WE#=H, output is High-Z. *9: Output is either Valid or High-Z depending on the level of UB# and LB# input. *10: Input is either Valid or Invalid depending on the level of UB# and LB# input. *11: Output is either High-Z or Invalid depending on the level of OE# and WE# input. *12: Keep the level from previous cycle except for suspending on last data. Refere to "WAIT# Output Function" in FUNCTIONAL DESCRIPTION for the details. *13: WAIT# output is driven in High level during write operation. 96 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary STATE DIAGRAM Initial/Standby State Power Up Asynchronous Operation (Page Mode) Synchronous Operation (Burst Mode) Pause Time Power Down CE2=L CR Set Common State Power Down CE2=L CE2=H Standby @M=1 @M=0 CE2=H Standby Asynchronous Operation CE2=CE#1=H Standby CE#1=L & WE#=L CE#1=L CE#1=H CE#1=H CE#1=L & OE#=L CE#1=H Output Disable WE#=H Byte Control Write WE#=L OE#=H OE#=L Read Address Change or Byte Control Byte Control @OE#=L Synchronous Operation CE2=CE#1=H Standby CE#1=H CE#1=H WE#=H WE#=L ADV# Low Pulse Write CE#1=H CE#1=H OE#=H OE#=L ADV# Low Pulse Write Suspend Read Suspend CE#1=L, CE#1=L, ADV# Low Pulse, ADV# Low Pulse, & OE#=L & WE#=L Read ADV# Low Pulse (@BL=8 or 16, and after burst operationis completed) Note: Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the FUNCTIONAL DESCRIPTION, AC CHARACTERISTICS, and TIMING DIAGRAM for details. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 97 Preliminary FUNCTIONAL DESCRIPTION This device supports asynchronous page read & normal write operation and synchronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as user configuable option. Power-up It is required to follow the power-up timing to start executing proper device operation. Refer to POWER-UP Timing. After Power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power down feature. Configuration Register The Configuration Register (CR) is used to configure the type of device function among optional features. Each selection of features is set through CR Set sequence after Power-up. If CR Set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration CR Set Sequence The CR Set requires total 6 read/write operation with unique address. Between each read/write operation requires that device being in standby mode. Following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 7FFFFFh (MSB) 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh Address Key Data Read Data (RDa) RDa RDa X X Read Data (RDb) The first cycle is to read from most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written into the different address, the CR Set is cancelled and the data written by the second or third cycle is valid as a normal write operation. The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is don't-care. If the forth or fifth cycle is written into different address, the CR Set is also cancelled but write data may not be written as normal write operation. The last cycle is to read from specific address key for mode selection. And read data (RDb) is invalid. Once this CR Set sequence is performed from an initial CR set to the other new CR set, the written data stored in memory cell array may be lost. So, it should perform the CR Set sequence prior to regular read/write operation if necessary to change from default configuration. 98 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary FUNCTIONAL DESCRIPTION (Continued) Address Key The address key has the following format. Address Pin A22-A21 Register Name -- Function -- Partial Size Key 1 00 01 10 11 000 001 010 Description Unused bits muse be 1 32M Partial 16M Partial Reserved for future use Sleep [Default] Reserved for future use Reserved for future use 8 words 16 words Reserved for future use Reserved for future use Reserved for future use Continuous Synchronous Mode (Burst Read / Write) Asynchronous Mode[Default] (Page Read / Normal Write) Reserved for future use 3 clocks 4 clocks 5 clocks Reserved for future use Reserved for future use Sequential Burst Read & Burst Write Burst Read & Single Write Falling Clock Edge Rising Clock Edge Unused bits muse be 1 WE# Single Clock Pulse Control without Write Suspend Function WE# Level Control with Write Suspend Function Unused bits muse be 1 Note *1 A20-A19 PS *2 *2 *2 A18-A16 BL Burst Length 011 100 101 110 111 0 *2 *2 *2 *3 *4 *2 A15 M Mode 1 000 001 010 011 1xx 0 1 0 1 0 1 1 0 A14-A12 RL Read Latency *2 *2 A11 A10 A9 A8 A7 A6-A0 BS SW VE -- WC -- Burst Sequence Single Write Valid Clock Edge -- Write Control *5 *1 *5 1 -- 1 *1 Notes *1: A22, A21, A8, and A6 to A0 must be all "1" in any cases. *2: It is prohibited to apply this key. *3: If M=0, all the registers must be set with appropriate Key input at the same time. *4: If M=1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs must be "1". *5: Burst Read & Single Write is not supported at WE# Single Clock Pulse Control. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 99 Preliminary FUNCTIONAL DESCRIPTION (Continued) Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode and mains low power idle state as long as CE2 is kept low. CE2 High resume the device from power down mode. This device has three power down modes, Sleep, 16M Partial, and 32M Partial. The selection of power down mode is set through CR Set sequence. Each mode has following data retention features. Mode Sleep [default] 16M Partial 32M Partial Data Retention Size No 16M bit 32M bit Retention Address N/A 000000h to 0FFFFFh 000000h to 1FFFFFh The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to perform CR Set sequence to set to Sleep mode after power-up in case of asynchronous operation. 100 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary FUNCTIONAL DESCRIPTION (Continued) Burst Read/Write Operation Synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or system bus frequency. Configuration Register Set is required to perform burst read & write operation after power-up. Once CR Set sequence is performed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through CR Set sequence together with operation mode. In order to perform synchronous burst read & write operation, it is required to control new signals, CLK, ADV# and WAIT# that Low Power SRAMs don't have. Burst Read Operation CLK ADDRESS ADV# CE#1 Valid OE# WE# DQ High RL High-Z Q1 BL WAIT# High-Z Q2 QBL Burst Write Operation CLK ADDRESS ADV# CE#1 High Valid OE# WE# DQ High-Z RL-1 D1 BL D2 DBL WAIT# High-Z June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 101 Preliminary FUNCTIONAL DESCRIPTION (Continued) CLK Input Function The CLK is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. The CLK input increments device internal address counter and the valid edge of CLK is referred for latency counts from address latch, burst write data latch, and burst read data out. During synchronous operation mode, CLK input must be supplied except for standby state and power down state. CLK is don't care during asynchronous operation. ADV# Input Function The ADV# is input signal to indicate valid address presence on address inputs. It is applicable to synchronous operation as well as asynchronous operation. ADV# input is active during CE#1=L and CE#1=H disables ADV# input. All the address are determined on the positive edge of ADV#. During synchronous burst read/write operation, ADV#=H disables all address inputs. Once ADV# is brought to High after valid address latch, it is inhibited to bring ADV# Low until the end of burst or until burst operation is terminated. ADV# Low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. During asynchronous operation, ADV#=H also disables all address inputs. ADV# can be tied to Low during asynchronous operation and it is not necessary to control ADV# to High. WAIT# Output Function The WAIT# is output signal to indicate data bus status when the device is operating in synchronous burst mode. During burst read operation, WAIT# output is enabled after specified time duration from OE#=L. WAIT# output Low indicates data out at next clock cycle is invalid, and WAIT# output becomes High one clock cycle prior to valid data out. During OE# read suspend, WAIT# output doesn't indicate data bus status but carries the same level from previous clock cycle (kept High) except for read suspend on the final data output. If final read data out is suspended, WAIT# output become high impedance after specified time duration from OE#=H. During burst write operation, WAIT# output is enabled to High level after specified time duration from WE#=L and kept High for entire write cycles including WE# write suspend. The actual write data latching starts on the appropriate clock edge with respect to Valid Click Edge, Read Latency and Burst Length. During WE# write suspend, WAIT# output doesn't indicate data bus status but carries the same level from previous clock cycle (kept High) except for write suspend on the final data input. If final write data in is suspended, WAIT# output become high impedance after specified time duration from WE#=H. This device doesn't incur additional delay against accrossing device-row boundary or internal refresh orepation. Therefore, the burst operation is always started after fixed latency with respect to Read Latency. And there is no waitting cycle asserted in the middle of burst operation except for burst suspend by OE# brought to High or WE# brought to High. Thus, once WAIT# output is enabled and brought to High, WAIT# output keep High level until the end of burst or until the burst operation is terminated. When the device is operating in asynchronous mode, WAIT# output is always in High Impedance. 102 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary FUNCTIONAL DESCRIPTION (Continued) Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through CR Set sequence after power-up. Once specific RL is set through CR Set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started after fixed latency with respect to Read Latency set in CR. CLK ADDRESS ADV# CE#1 OE# or WE# RL=3 DQ [Out] WAIT# DQ [In] WAIT# High-Z RL=4 DQ [Out] WAIT# DQ [In] WAIT# High-Z RL=5 DQ [Out] WAIT# DQ [In] WAIT# High-Z High-Z D1 D2 D3 D4 Q1 Q2 Q3 High-Z D1 D2 D3 D4 D5 Q1 Q2 Q3 Q4 High-Z D1 D2 D3 D4 D5 D5 Q1 Q2 Q3 Q4 Q5 0 Valid 1 2 3 4 5 6 June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 103 Preliminary FUNCTIONAL DESCRIPTION (Continued) Address Latch by ADV# The ADV# indicates valid address presence on address inputs. During synchronous burst read/write operation mode, all the address are determined on the positive edge of ADV# when CE#1=L. The specified minimum value of ADV#=L setup time and hold time against valid edge of clock where RL count begin must be satisfied for appropriate RL counts. Valid address must be determined with specified setup time against either the negative edge of ADV# or negative edge of CE#1 whichever comes late. And the determined valid address must not be changed during ADV#=L period. Burst Length Burst Length is the number of word to be read or write during synchronous burst read/write operation as the result of a single address latch cycle. It can be set on 8, 16 words boundary or continuous for entire address through CR Set sequence. The burst type is sequential that is incremental decoding scheme within a boundary address. Starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (=0). After completing read data out or write data latch for the set burst length, operation automatically ended except for continuous burst length. When continuous burst length is set, read/write is endless unless it is terminated by the positive edge of CE#1. Single Write Single Write is synchronous write operation with Burst Length =1. The device can be configured either to "Burst Read & Single Write" or to "Burst Read & Burst Write" through CR set sequence. Once the device is configured to "Burst Read & Single Write" mode, the burst length for syncronous write operation is always fixed 1 regardless of BL values set in CR, while burst length for read is in accordance with BL values set in CR. 104 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary Write Control The device has two type of WE# signal control method, "WE# Level Control" and "WE# Single Clock Pulse Control", for synchronous write operation. It is configured through CR set sequence. CLK ADDRESS ADV# CE#1 WE# Level Control WE# DQ [In] WAIT# High-Z tWLTH tWLD D1 D2 D3 D4 RL=5 0 Valid 1 2 3 4 5 6 WE# Single Clock Pulse Control WE# DQ [In] WAIT# High-Z tWSCK tCKWH D1 tWLTH DQ2 D3 D4 June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 105 Preliminary FUNCTIONAL DESCRIPTION (Continued) Burst Read Suspend Burst read operation can be suspended by OE# High pulse. During burst read operation, OE# brought to High suspends burst read operation. Once OE# is brought to High with the specified set up time against clock where the data being suspended, the device internal counter is suspended, and the data output become high impedance after specified time duration. It is inhibited to suspend the first data out at the beginning of burst read. OE# brought to Low resumes burst read operation. Once OE# is brought to Low, data output become valid after specified time duration, and internal address counter is reactivated. The last data out being suspended as the result of OE#=H and first data out as the result of OE#=L are the from the same address. CLK tCKOH tOSCK OE# tCKOH tOSCK tAC DQ tCKTV WAIT# Q1 tCKQX tOHZ Q2 tOLZ tAC tAC Q2 tAC Q3 Q4 tCKQX tCKQX Burst Write Suspend Burst write operation can be suspended by WE# High pulse. During burst write operation, WE# brought to High suspends burst write operation. Once WE# is brought to High with the specified set up time against clock where the data being suspended, device internal counter is suspended, data input is ignored. It is inhibited to suspend the first data input at the beginning of burst write. WE# brought to Low resumes burst write operation. Once WE# is brought to Low, data input become valid after specified time duration, and internal address counter is reactivated. The write address of the cycle where data being suspended and the first write address as the result of WE#=L are the same address. Burst write suspend function is available when the device is operating in WE# level controlled burst write only. CLK tCKWHtWSCK WE# tCKWHtWSCK tDSCK DQ D1 tDHCK WAIT# High D2 tDDSCK D2 tDDSCK D3 tDSCK D4 tDHCK tDHCK 106 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary FUNCTIONAL DESCRIPTION (Continued) Burst Read Termination Burst read operation can be terminated by CE#1 brought to High. If BL is set on Continuous, burst read operation is continued endless unless terminated by CE#1=H. It is inhibited to terminate burst read before first data out is completed. In order to guarantee last data output, the specified minimum value of CE#1=L hold time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new access. CLK ADDRESS ADV# tCKCLH CE#1 tCKOH OE# WAIT# DQ tAC Q1 Q2 High-Z tCKQX tOHZ tCHZ tTRB Valid Burst Write Termination Burst write operation can be terminated by CE#1 brought to High. If BL is set on Continuous, burst write operation is continued endless unless terminated by CE#1=H. It is inhibited to terminate burst write before first data in is completed. In order to guarantee last write data being latched, the specified minimum values of CE#1=L hold time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new access. CLK ADDRESS ADV# tCKCLH CE#1 tCKWH WE# WAIT# DQ High-Z D2 tDHCK tCHZ tTRB Valid tDD1 tD- tDHCK June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 107 Preliminary ABSOLUTE MAXIMUM RATINGS (See WARNING below.) Parameter Voltage of VDD Supply Relative to VSS Voltage of VDDQ Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage Temperature Symbol VDD VDDQ VIN, VOUT IOUT TSTG Value -0.5 to +3.6 -0.5 to +2.6 -0.5 to +2.6 +50 -55 to +125 Unit V V V mA o C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS (See WARNING below.) (Referenced to VSS) Parameter Supply Voltage DQ Supply Voltage Ground High Level Input Voltage Low Level Input Voltage Ambient Temperature *1 *2 Notes Symbol VDD VDDQ VSS VIH VIL TA Min. 2.6 1.65 0 VDDQ*0.8 -0.3 -30 Max. 3.1 1.95 0 VDDQ+0.2 VDDQ*0.2 85 Unit V V V V V C Notes *1: Maximum DC voltage on input and DQ pins are VDDQ+0.2V. During voltage transitions, inputs may positive overshoot to VDDQ+1.0V for periods of up to 5 ns. *2: Minimum DC voltage on input or DQ pins are -0.3V. During voltage transitions, inputs may negative overshoot VSS to -1.0V for periods of up to 5ns. device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the 108 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary DC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted)Note *1,*2,*3 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Symbol ILI ILO VOH VOL IDDPS Test Conditions VIN = VSS to VDDQ VOUT = VSS to VDDQ, Output Disable VDDQ = VDDQ(min), IOH = -0.5mA IOL = 1mA VDD = VDD max., VDDQ = VDDQ max., VIN = VIH or VIL, CE2 0.2V SLEEP 16M Partial 32M Partial Min. -1.0 -1.0 1.4 -- -- -- -- Max. +1.0 +1.0 -- 0.4 10 120 150 Unit A A V V A A A VDD Power Down Current IDDP16 IDDP32 IDDS VDD = VDD max., VDDQ = VDDQ max., VIN (including CLK)= VIH or VIL , CE#1 = CE2 = VIH VDD = VDD max., VDDQ = VDDQ max., VIN (including CLK) 0.2V or VIN (including CLK) VDDQ - 0.2V, CE#1 = CE2 VDDQ - 0.2V VDD = VDD max., VDDQ = VDDQ max., tCK=min. VIN 0.2V or VIN VDDQ - 0.2V, CE#1 = CE2 VDDQ - 0.2V VDD = VDD max., VDDQ = VDDQ max., VIN = VIH or VIL, CE#1 = VIL and CE2= VIH, IOUT=0mA tRC / tWC = minimum tRC / tWC = 1s -- 1.5 mA VDD Standby Current IDDS1 -- 300 A IDDS2 -- 350 A IDDA1 VDD Active Current IDDA2 -- 35 mA -- 5 mA VDD Page Read Current IDDA3 VDD = VDD max., VDDQ = VDDQ max., VIN = VIH or VIL, CE#1 = VIL and CE2= VIH, IOUT=0mA, tPRC = min. VDD = VDD max., VDDQ = VDDQ max., VIN = VIH or VIL, CE#1 = VIL and CE2= VIH, tCK = tCK min., BL = Continuous, IOUT=0mA, -- 15 mA VDD Burst Access Current IDDA4 -- 30 mA Notes *1: All voltages are referenced to Vss. *2: DC Characteristics are measured after following POWER-UP timing. *3: IOUT depends on the output load conditions. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 109 Preliminary AC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted) ASYNCHRONOUS READ OPERATION (PAGE MODE) Parameter Read Cycle Time CE#1 Access Time OE# Access Time Address Access Time ADV# Access Time LB#, UB# Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE#1 Low to Output Low-Z OE# Low to Output Low-Z LB#, UB# Low to Output Low-Z CE#1 High to Output High-Z OE# High to Output High-Z LB#, UB# High to Output High-Z Address Setup Time to CE#1 Low Address Setup Time to OE# Low ADV# Low Pulse Width Address Hold Time from ADV# High Address Invalid Time Address Hold Time from CE#1 High Address Hold Time from OE# High CE#1 High Pulse Width Symbol tRC tCE tOE tAA tAV tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tVPL tAHV tAX tCHAH tOHAH tCP Value Min. 70 -- -- -- Max. 1000 70 40 70 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes *1, *2 *3 *3 *3, *5 *3 *3 *3, *6 *1, *6, *7 *3 *4 *4 *4 *3 *3 *3 -- -- 20 5 5 0 0 -- -- -- -5 10 10 5 -- -5 -5 15 30 20 1000 -- -- -- -- 20 20 20 -- -- -- -- 10 -- -- -- *8 *5, *9 *10 Notes *1: Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A22. If needed by system operation, please contact local FUJITSU representative for the relaxation of 1ms limitation. *2: Address Should Not Be Changed Within Minimum Trc. *3: The output load 50pF with 50ohm termination to VDDQ*0.5 V. *4: The output load 5pF without any other load. *5: Applicable to A3 to A22 when CE#1 is kept at Low. *6: Applicable only to A0, A1 and A2 when CE#1 is kept at Low for the page address access. *7: In case Page Read Cycle is continued with keeping CE#1 stays Low, CE#1 must be brought to High within 4ms. In other words, Page Read Cycle must be closed within 4ms. *8: tVPL is specified from the negative edge of either CE#1 or ADV# whichever comes late. *9: Applicable when at least two of address inputs among applicable are switched from previous state. *10: tRC(min) and tPRC(min) must be satisfied. 110 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary AC CHARACTERISTICS (Continued) ASYNCHRONOUS WRITE OPERATION Parameter Write Cycle Time Address Setup Time ADV# Low Pulse Width Address Hold Time from ADV# High CE#1 Write Pulse Width WE# Write Pulse Width LB#, UB# Write Pulse Width CE#1 Write Recovery Time WE# Write Recovery Time LB#, UB# Write Recovery Time Data Setup Time Data Hold Time OE# High to CE#1 Low Setup Time for Write OE# High to Address Setup Time for Write LB#, UB# Write Pulse Overlap CE#1 High Pulse Width Symbol tWC tAS tVPL tAHV tCW tWP tBW tWRC tWR tBR tDS tDH tOHCL tOES tBWO tCP Value Min. 70 0 10 5 45 45 45 15 15 15 15 0 -5 0 30 15 Max. 1000 -- -- -- -- -- -- -- 1000 1000 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes *1, *2 *3 *4 *3 *3 *3 *5 *5 *5 *6 *7 Notes *1: Maximum value is applicable if CE#1 is kept at Low without any address change. If the relaxation is needed by system operation, please contact local FUJITSU representative for the relaxation of 1ms limitation. *2: Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWRC, tWR or tBR). *3: Write pulse is defined from High to Low transition of CE#1, WE# or LB# / UB#, whichever occurs last. *4: tVPL is specified from the negative edge of either CE#1 or ADV# whichever comes late. *5: Write recovery is defined from Low to High transition of CE#1, WE# or LB# / UB#, whichever occurs first. *6: If OE# is Low after minimum tOHCL , read cycle is initiated. In other word, OE# must be brought to High within 5ns after CE#1 is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. *7: If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data bus is in High-Z. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 111 Preliminary AC CHARACTERISTICS (Continued) SYNCHRONOUS OPERATION - CLOCK INPUT (BURST MODE) Parameter RL=5 Clock Period RL=4 RL=3 Clock High Time Clock Low Time Clock Rise/Fall Time tCKH tCKL tCKT tCK Symbol Value Min. 13 18 30 4 4 -- Max. -- -- -- -- -- 3 Unit ns ns ns ns ns ns Notes *1 *1 *1 *2 Notes *1: Clock period is defined between valid clock edge. *2: Clock rise/fall time is defined between VIH Min. and VIL Max. SYNCHRONOUS OPERATION - ADDRESS LATCH (BURST MODE) Parameter Address Setup Time to ADV# Low Address Setup Time to CE#1 Low Address Hold Time from ADV# High ADV# Low Pulse Width ADV# Low Setup Time to CLK ADV# Low Setup Time to CE#1 Low CE#1 Low Setup Time to CLK ADV# Low Hold Time from CLK Burst End ADV High Hold Time from CLK Symbol tASVL tASCL tAHV tVPL tVSCK tVLCL tCLCK tCKVH tVHVL Value Min. -5 -5 5 10 5 5 5 1 13 Max. -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns Notes *1 *1 *2 *3 *1 *3 *3 Notes *1: tASCL is applicable if CE#1 brought to Low after ADV# is brought to Low under the condition where tVLCL is satisfied. The both of tASCL and tASVL must be satisfied if tVLCL is not satisfied. *2: tVPL is specified from the negative edge of either CE#1 or ADV# whichever comes late. *3: Applicable to the 1st valid clock edge. 112 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary AC CHARACTERISTICS (Continued) SYNCHRONOUS READ OPERATION (BURST MODE) Parameter Burst Read Cycle Time CLK Access Time Output Hold Time from CLK CE#1 Low to WAIT# Low OE# Low to WAIT# Low ADV# Low to WAIT# Low CLK to WAIT# Valid Time WAIT# Valid Hold Time from CLK CE#1 Low to Output Low-Z OE# Low to Output Low-Z LB#, UB# Low to Output Low-Z CE#1 High to Output High-Z OE# High to Output High-Z LB#, UB# High to Output High-Z CE#1 High to WAIT# High-Z OE# High to WAIT# High-Z OE# Low Setup Time to 1st Data-out UB#, LB# Setup Time to 1st Data-out OE# Setup Time to CLK OE# Hold Time from CLK Burst End CE#1 Low Hold Time from CLK Burst End UB#, LB# Hold Time from CLK Burst Terminate Recovery Time BL=8,16 BL=Continuous Symbol tRCB tAC tCKQX tCLTL tOLTL tVLTL tCKTV tCKTX tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tCHTZ tOHTZ tOLQ tBSQ tOSCK tCKOH tCKCLH tCKBH tTRB Value Min. -- -- 3 5 0 0 -- 3 5 0 0 -- -- -- -- -- 30 26 5 5 5 5 26 70 Max. 8000 11 -- 20 20 20 11 -- -- -- -- 20 20 20 20 20 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *4 *4 *3 *1 *1 *1 *1 *1 *1 *1 *2 *2 *2 *1 *1 *1 *1 *1 Notes Notes *1: The output load 50pF with 50ohm termination to VDDQ*0.5 V. *2: The output load 5pF without any other load. *3: Once they are determined, they must not be changed until the end of burst. *4: Defined from the Low to High transition of CE#1 to the High to Low transition of either ADV# or CE#1 whichever occurs late. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 113 Preliminary AC CHARACTERISTICS (Continued) SYNCHRONOUS WRITE OPERATION (BURST MODE) Parameter Burst Write Cycle Time Data Setup Time to Clock Data Hold Time from CLK WE# Low Setup Time to 1st Data In UB#, LB# Setup Time for Write WE# Setup Time to CLK WE# Hold Time from CLK CE#1 Low to WAIT# High WE# Low to WAIT# High CE#1 High to WAIT# High-Z WE# High to WAIT# High-Z Burst End CE#1 Low Hold Time from CLK Burst End CE#1 High Setup Time to next CLK Burst End UB#, LB# Hold Time from CLK Burst Write Recovery Time Burst Terminate Recovery Time BL=8,16 BL=Continuous Symbol tWCB tDSCK tDHCK tWLD tBS tWSCK tCKWH tCLTH tWLTH tCHTZ tWHTZ tCKCLH tCHCK tCKBH tWRB tTRB tTRB Value Min. -- 5 3 30 -5 5 5 5 0 -- -- 5 5 5 26 26 70 -- -- Max. 8000 -- -- -- -- -- -- 20 20 20 20 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes *1 *2 *2 *2 *2 *3 *4 *4 Notes *1: Defined from the valid input edge to the High to Low transition of either ADV#, CE#1, or WE#, whichever occurs last. And once they are determined, they must not be changed until the end of burst. *2: The output load 50pF with 50ohm termination to VDDQ*0.5 V. *3: Defined from the valid clock edge where last data-in being latched at the end of burst write to the High to Low transition of either ADV# or CE#1 whichever occurs late for the next access. *4: Defined from the Low to High transition of CE#1 to the High to Low transition of either ADV# or CE#1 whichever occurs late for the next access. 114 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary AC CHARACTERISTICS (Continued) POWER DOWN PARAMETERS Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE#1 High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] CE#1 High Hold Time following CE2 High after Power Down Exit [not in SLEEP mode] CE#1 High Setup Time following CE2 High after Power Down Exit Symbol tCSP tC2LP tCHH tCHHP tCHS Value Min. 20 70 300 1 0 Max. -- -- -- -- -- Unit ns ns s s s Note *1 *1 *1 *2 *1 Notes *1: Applicable also to power-up. *2: Applicable when Partial mode is set. OTHER TIMING PARAMETERS Parameter CE#1 High to OE# Invalid Time for Standby Entry CE#1 High to WE# Invalid Time for Standby Entry CE2 High Hold Time after Power-up CE#1 High Hold Time following CE2 High after Power-up Input Transition Time (except for CLK) Symbol tCHOX tCHWX tC2HL tCHH tT Value Min. 10 10 50 300 1 Max. -- -- -- -- 25 Unit ns ns s s s Note *1 *2, *3 Notes *1: Some data might be written into any address location if tCHWX(min) is not satisfied. *2: Except for clock input transition time. *3: The Input Transition Time (tT) at AC testing is shown in below. If actual tT is longer than specified values, it may violate AC specification of some timing parameters. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 115 Preliminary AC CHARACTERISTICS (Continued) AC TEST CONDITIONS Symbol VIH VIL VREF tT Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Async. Sync. Test Setup Value VIOPS * 0.8 VIOPS * 0.2 VIOPS * 0.5 Unit V V V ns ns Note Between VIL and VIH 5 3 AC MEASUREMENT OUTPUT LOAD CIRCUIT VDDQ*0.5V VCCPS VSS VCCPS VSS 0.1F DEVICE UNDER TEST 50pF 50ohm OUT 0.1F 116 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS Asynchronous Read Timing #1-1 (Basic Timing). tRC ADDRESS ADDRESS VALID ADV# Low tASC tCE tCHAH tCP tOE tCHZ tOHZ tBHZ tASC CE#1 OE# tBA tOLZ tBLZ LB# / UB# DQ (Output) VALID DATA OUTPUT tOH Note:This timing diagram assumes CE2=H and WE#=H. Asynchronous Read Timing #1-2 (Basic Timing) tRC ADDRESS ADDRESS VALID tAV ADV# tASC CE#1 tOE OE# tBA tOLZ tBLZ tOHZ tBHZ tVPL tCE tCP tCHZ tASC tAHV LB# / UB# DQ (Output) VALID DATA OUTPUT tOH Note:This timing diagram assumes CE2=H and WE#=H. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 117 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Read Timing #2 (OE# & Address Access) tRC ADDRESS ADDRESS VALID tAA CE#1 Low tASO OE# tOE tAx tRC ADDRESS VALID tAA tOHAH LB# / UB# tOLZ DQ (Output) VALID DATA OUTPUT VALID DATA OUTPUT tOH tOH tOHZ Notes:This timing diagram assumes CE2=H, ADV#=L and WE#=H. Asynchronous Read Timing #3 (LB# / UB# Byte Access) tAX ADDRESS tAA CE#1, Low tBA LB# tBA UB# tBLZ DQ0-7 (Output) DQ8-15 (Output) VALID DATA OUTPUT tBLZ VALID DATA OUTPUT tOH tBHZ tBHZ tOH tBLZ tBHZ tOH tBA tRC ADDRESS VALID tAx VALID DATA OUTPUT Note:This timing diagram assumes CE2=H, ADV#=L and WE#=H. 118 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Read Timing #4 (Page Address Access after CE#1 Control Access) tRC ADDRESS (A22-A3) tRC ADDRESS (A2-A0) ADV# CE#1 OE# LB# / UB# tCLZ DQ (Output) VALID DATA OUTPUT (Normal Access) Notes:This timing diagram assumes CE2=H and WE#=H. ADDRESS VALID tPRC ADDRESS VALID tPRC ADDRESS VALID tPRC ADDRESS VALID ADDRESS VALID tASC tPAA tPAA tPAA tCHAH tCHZ tCE tOH tOH tOH tOH VALID DATA OUTPUT (Page Access) Asynchronous Read Timing #5 (Random and Page Address Access) tRC ADDRESS (A22-A3) ADDRESS (A2-A0) CE#1 Low tASO OE# tBA LB# / UB# DQ (Output) tOLZ tBLZ tOH tOH tOH tOH tOE ADDRESS VALID tRC ADDRESS VALID tAX tRC ADDRESS VALID tAx tPRC ADDRESS VALID tRC ADDRESS VALID tPRC ADDRESS VALID tAA tPAA tAA tPAA VALID DATA OUTPUT (Normal Access) VALID DATA OUTPUT (Page Access) Notes *1: This timing diagram assumes CE2=H, ADV#=L and WE#=H. *2: Either or both LB# and UB# must be Low when both CE#1 and OE# are Low. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 119 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Write Timing #1-1 (Basic Timing) tWC ADDRESS ADV# Low tAS CE#1 tAS WE# tAS LB#, UB# tOHCL OE# DQ (Input) VALID DATA INPUT Notes:This timing diagram assumes CE2=H and ADV#=L. ADDRESS VALID tCW tWRC tAS tWP tWR tAS tBW tBR tAS tDS tDH Asynchronous Write Timing #1-2 (Basic Timing) tWC ADDRESS ADV# tAS CE#1 tAS WE# tAS LB#, UB# tOHCL OE# DQ (Input) VALID DATA INPUT Notes:This timing diagram assumes CE2=H. ADDRESS VALID tVPL tAHV tCW tWRC tAS tWP tWR tAS tBW tBR tAS tDS tDH 120 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Write Timing #2 (WE# Control) tWC ADDRESS tOHAH CE#1 Low tAS WE# tWP tWR tAS tWP tWR ADDRESS VALID tWC ADDRESS VALID LB#, UB# tOES OE# tOHZ DQ (Input) VALID DATA INPUT VALID DATA INPUT tDS tDH tDS tDH Note:This timing diagram assumes CE2=H and ADV#=L. Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control) tWC ADDRESS CE#1 Low tAS WE# tBR LB# tBR UB# DQ0-7 (Input) DQ8-15 (Input) tDS tDH tWP tAS tWP ADDRESS VALID tWC ADDRESS VALID VALID DATA INPUT tDS tDH VALID DATA INPUT Note:This timing diagram assumes CE2=H, ADV#=L and OE#=H. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 121 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control) tWC ADDRESS CE#1 Low tWR WE# tAS LB# tAS UB# tDS DQ0-7 (Input) VALID DATA INPUT DQ8-15 (Input) tDH tBW tBW tWR ADDRESS VALID tWC ADDRESS VALID tDS tDH VALID DATA INPUT Note:This timing diagram assumes CE2=H, ADV#=L and OE#=H. Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control) tWC ADDRESS CE#1 Low ADDRESS VALID tWC ADDRESS VALID WE# tAS LB# tAS UB# tDS DQ0-7 (Input) VALID DATA INPUT DQ8-15 (Input) tDS tDH tDH tBW tBR tBW tBR VALID DATA INPUT Note:This timing diagram assumes CE2=H, ADV#=L and OE#=H. 122 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control) tWC ADDRESS CE#1 Low ADDRESS VALID tWC ADDRESS VALID WE# tAS LB# DQ1-8 (Input) tAS UB# DQ9-16 (Input) tDS tDH tBWO tDS tBW tDH tDS tDH tBW tBR tAS tBW tBR VALID DATA INPUT VALID DATA INPUT tBR tAS tBW tBWO tDS tBR tDH VALID DATA INPUT VALID DATA INPUT Note:This timing diagram assumes CE2=H, ADV#=L and OE#=H. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 123 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Read / Write Timing #1-1 (CE#1 Control) tWC ADDRESS tCHAH CE#1 tCP WE# tCP tAS WRITE ADDRESS tCW tWRC tASC tRC READ ADDRESS tCE tCHAH UB#, LB# tOHCL OE# tCHZ tOH tDS tDH tCLZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT Notes *1: This timing diagram assumes CE2=H and ADV#=L. *2: Write address is valid from either CE#1 or WE# of last falling edge. Asynchronous Read / Write Timing #1-2 (CE#1 / WE# / OE# Control) tWC ADDRESS tCHAH CE#1 tCP tAS WRITE ADDRESS tWR tCP tASC tRC READ ADDRESS tCE tCHAH tWP WE# UB#, LB# tOHCL OE# tCHZ tOH tOE tDS tDH tOLZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT Notes *1: This timing diagram assumes CE2=H and ADV#=L. *2: OE# can be fixed Low during write operation if it is CE#1 controlled write at Read-Write-Read sequence. 124 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Asynchronous Read / Write Timing #2 (OE#, WE# Control) tWC ADDRESS tOHAH CE#1 Low tAS WE# tOES tWP tWR WRITE ADDRESS tRC READ ADDRESS tAA tOHAH UB#, LB# tASO OE# tOHZ tOH tOE tOHZ tOH tDS tDH tOLZ DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT Notes *1: This timing diagram assumes CE2=H and ADV#=L. *2: CE#1 can be tied to Low for WE# and OE# controlled operation. Asynchronous Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) tWC ADDRESS WRITE ADDRESS tRC READ ADDRESS tAA CE#1 Low tOHAH tOHAH WE# tOE UB#, LB# tBHZ OE# tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tBLZ tASO tBHZ tOH tAS tBW tBR tBA Notes *1: This timing diagram assumes CE2=H and ADV#=L. *2: CE#1 can be tied to Low for WE# and OE# controlled operation. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 125 Preliminary TIMING DIAGRAMS (Continued) Clock Input Timing tCK CLK tCK tCKH tCKL tCKT tCKT Notes *1: Stable clock input must be required during CE#1=L. *2: tCK is defined between valid clock edge. *3: tCKT is defined between VIH Min. and VIL Max. Address Latch Timing (Synchronous Mode) Case #1 CLK Case #2 ADDRESS tASCL Valid tCKVH tVSCK tAHV tASVL Valid tVSCK tCKVH tAHV ADV# tVLCL tCLCK tVPL tVPL CE#1 Low Notes *1: Case #1 is the timing when CE#1 is brought to Low after ADV# is brought to Low. Case #2 is the timing when ADV# is brought to Low after CE#1 is brought to Low. *2: tVPL is specified from the negative edge of either CE#1 or ADV# whichever comes late. At least one valid clock edge must be input during ADV#=L. *3: tVSCK and tCLCK are applied to the 1st valid clock edge during ADV#=L. 126 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Synchronous Read Timing #1 (OE# Control) RL=5 CLK tRCB ADDRESS tASVL ADV# tVPL tASCL CE#1 tCLCK OE# tOLQ WE# High tCKBH LB#, UB# tBLQ tCKTV WAIT# High-Z tOLTL DQ High-Z tOLZ tCKTX tAC tAC Q1 tCKQX tAC QBL tCKQX tOHZ tOHTZ tCKOH tCLCK tVHVL tASCL tVPL Valid tVSCK tAHV tCKVH tASVL Valid tVSCK tCKVH tCP Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 127 Preliminary TIMING DIAGRAMS (Continued) Synchronous Read Timing #2 (CE#1 Control) RL=5 CLK tRCB ADDRESS tASVL ADV# tVPL tASCL CE#1 tCLCK OE# tVHVL tASCL tCP tCKCLH tCLCK tVPL Valid tVSC tAHV tCKVH tASVL Valid tVSCK tAHV tCKVH WE# High tCKBH LB#, UB# tCKTV WAIT# tCLTL DQ tCLZ tCKTX tAC tAC Q1 tCKQX tAC QBL tCKQX tCHZ tCLZ tCHTZ tCLTL Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. 128 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Synchronous Read Timing #3 (ADV# Control) RL=5 CLK tRCB ADDRESS tASVL ADV# tVPL tVHVL tVPL Valid tVSCK tAHV tCKVH tASVL Valid tVSCK tAHV tCKVH CE#1 Low OE# Low WE# High LB#, UB# tCKTV tVLTL RDY tCKTX DQ tAC tAC Q1 tCKQX tAC QBL tCKQX tVLTL Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 129 Preliminary TIMING DIAGRAMS (Continued) Synchronous Write Timing #1 (WE# Level Control) RL=5 CLK tWCB ADDRESS tASVL ADV# tVPL tASCL CE#1 tCLCK OE# High tWLD WE# tBS LB#, UB# tCKBH tBS tCKWH tCP Valid tVSCK tAHV tCKVH tVHVL tWRB tASCL tVPL tCLCK tASVL Valid tVSC tAHV tCKVH RDY High-Z tWLTH tDSCK D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tWHTZ DQ Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. 130 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Synchronous Write Timing #2 (WE# Single Clock Pulse Control) RL=5 CLK tWCB ADDRESS tASVL ADV# tVPL tASCL CE#1 tCLCK OE# High tWSCK tCKWH WE# tBS LB#, UB# tCKBH tBS tWSCK tCKWH tCP tCKCLH Valid tVSCK tAHV tCKVH tVHVL tWRB tASCL tVPL tCLCK tASVL Valid tVSCK tAHV tCKVH WAIT# High-Z tWLTH DQ tDSCK D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tCHTZ tWLTH Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 131 Preliminary TIMING DIAGRAMS (Continued) Synchronous Write Timing #3 (ADV# Control) RL=5 CLK tWCB ADDRESS tASVL ADV# tVPL Valid tVSCK tAHV tCKVH tVHVL tASVL Valid tVSCK tAHV tCKVH tVPL CE#1 tWRB OE# High WE# tBS LB#, UB# tCKBH tBS WAIT# High tDDQ D1 tDD2 tDDBL tDHCK tDHCK Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. 132 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Synchronous Write Timing #4 (WE# Level Control, Single Write) RL=5 CLK tWCB ADDRESS tASVL ADV# tVPL tASCL CE#1 tCLCK OE# High tWLD WE# tBS LB#, UB# tCKBH tBS tCKWH tCP Valid tVSCK tAHV tCKVH tVHVL tWRB tASCL tVPL tCLCK tASVL Valid tVSCK tAHV tCKVH WAIT# High-Z tWLTH tDSCK D1 tDHCK tWHTZ tWLTH DQ Notes *1: This timing diagram assumes CE2=H, the valid clock edge on rising edge and single write operation. *2: Write data is latched on the valid clock edge. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 133 Preliminary TIMING DIAGRAMS (Continued) Synchronous Read to Write Timing #1(CE#1 Control) RL=5 CLK tWCB ADDRESS tASVL ADV# tCKCLH CE#1 tCP OE# Valid tVSCK tAHV tCKVH tVPL tCLCK tCKCLH tVHVL tASCL WE# tCKBH LB#, UB# tCHTZ WAIT# tAC DQ QBL-1 tCKQX QBL tCKQX tCHZ tCLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tBS tCKBH Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. 134 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Synchronous Read to Write Timing #2(ADV# Control) RL=5 CLK ADDRESS tASVL ADV# Valid tVSCK tAHV tCKVH tVPL tVHVL CE#1 tCKOH OE# tWLD WE# tCKBH LB#, UB# tOHTZ WAIT# tAC DQ QBL-1 tCKQX QBL tCKQX tOHZ tWLTH tDSCK D1 tDHCK tDSCK D2 tDHCK tDSCK D3 tDHCK tDSCK DBL tDHCK tBS tCKBH tCKWH Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 135 Preliminary TIMING DIAGRAMS (Continued) Synchronous Write to Read Timing #1 (CE#1 Control) RL=5 CLK ADDRESS tASVL ADV# Valid tVSCK tAHV tCKVH tVPL tCKCLH tASCL tCP tWRB tCLCK CE#1 OE# WE# tCKBH LB#, UB# tCKTV WAIT# tDSCK DQ tDSCK DBL tDHCK tCLZ tCHTZ High-Z tCLTL tCKTX tAC tAC Q1 tCKQX Q2 tCKQX DBL-1 tDHCK Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. 136 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Synchronous Write to Read Timing #2 (ADV# Control) RL=5 CLK ADDRESS tASVL ADV# tWRB CE#1 Low Valid tVSCK tAHV tCKVH tVPL OE# tCKWH WE# tCKBH LB#, UB# tCKTV WAIT# tDSCK DQ tDSCK DBL tDHCK tOLZ tWHTZ High-Z tOLTL tCKTX tAC tAC Q1 tCKQX Q2 tCKQX tBLQ tOLQ DBL-1 tDHCK Note:This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 137 Preliminary TIMING DIAGRAMS (Continued) POWER-UP Timing #1 CE#1 *2 tCHH *3 CE2 *2 VIOPS 0V VCCPS 0V VIOPS min *1 VCCPS min *1,*2 Notes *1: VDDQ shall be applied and reach the specified minimum level prior to VDD applied. *2: The both of CE#1 and CE2 shall be brought to High together with VDDQ prior to VDD applied. Otherwise POWER-UP Timing#2 must be applied for proper operation. *3: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE#1 and CE2. POWER-UP Timing #2 CE#1 *3 tC2HL *2 CE2 tC2HL VIOPS 0V VCCPS 0V VCCPS min *1 VIOPS min *1 *2 tCSP tC2LP tCHS tCHH Notes *1: VDDQ shall be applied and reach specified minimum level prior to VDD applied. *2: The tC2HL specifies from CE2 Low to High transition after VDD reaches specified minimum level. If CE2 became High prior to VDD reached specified minimum level, tC2HL is defined from VDD minimum. *3: CE#1 shall be brought to High prior to or together with CE2 Low to High transition. 138 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) POWER DOWN Entry and Exit Timing CE#1 tCHS CE2 tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP) Note:This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down program was not performed prior to this reset. Standby Entry Timing after Read or Write CE#1 tCHO OE# tCHWX WE# Active (Read) Standby Active (Write) Standby Note:Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period for Standby mode from CE#1 Low to High transition. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 139 Preliminary TIMING DIAGRAMS (Continued) Configuration Register Set Timing #1 (Asynchronous Operation) tRC ADDRESS MSB*1 tCP CE#1 tWC MSB*1 tCP tWC MSB*1 tCP tWC MSB*1 tCP tWC MSB*1 tCP tRC Key*2 tCP*3 (tRC) OE# WE# LB#, UB# DQ*3 RDa Cycle #1 RDa Cycle #2 RDa Cycle #3 X Cycle #4 X Cycle #5 RDb Cycle #6 Notes *1: The all address inputs must be High from Cycle #1 to #5. *2: The address key must confirm the format specified in FUNCTIONAL DESCRIPTION. If not, the operation and data are not guaranteed. *3: After tCP or tRC following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. tCP and tRC are applicable to returning to asynchronous mode and to synchronous mode respectively. 140 128Mb pSRAM S71WS512NE0BFWZZ_00_A1 June 28, 2004 Preliminary TIMING DIAGRAMS (Continued) Configuration Register Set Timing #2 (Synchronous Operation) CLK ADDRESS MSB tRCB ADV# tTRB MSB tWCB MSB tWCB MSB tWCB MSB tWCB Key tRCB tTRB tTRB tTRB tTRB tTRB CE#1 OE# WE# LB#, UB# RL DQ RDa Cycle#1 RL-1 RDa Cycle#2 RL-1 RDa Cycle#3 RL-1 X Cycle#4 RL-1 X Cycle#5 RL RDb Cycle#6 Notes *1: The all address inputs must be High from Cycle #1 to #5. *2: The address key must confirm the format specified in FUNCTIONAL DESCRIPTION. If not, the operation and data are not guaranteed. *3: After tTRB following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. June 28, 2004 S71WS512NE0BFWZZ_00_A1 128Mb pSRAM 141 Preliminary Revision Summary Revision A (April 27, 2004) Initial release. Revision A+1 (June 28, 2004) Modify Colophon & Company name. Trademarks and Notice The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004 Spansion LLC. All rights reserved. SpansionTM, the SpansionTM logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 142 Revision Summary S71WS512NE0BFWZZ_00_A1 June 28, 2004 |
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